# Calculate thermal noise power of receiver

My primary question (addressed at the end of this post) is that I have a voltage noise at the input to an ADC that I'd like to convert to a noise power. The remainder of this post details how I arrived at this voltage noise and why I'm having trouble converting it to a power level.

I'm attempting to calculate the thermal noise power of a receiver (at the input to an ADC). This is for a radar application where I'll use this noise power plus a minimum SNR to calculate the minimum detectable signal power, which I can use in turn to calculate the maximum range of the radar using the radar range equation. To calculate the noise power at the antenna, I use $$\P=kTB\$$. To determine the bandwidth, I take the frequency bin resolution of my downstream FFT, which is $$\1.953\,\text{kHz}\$$. I've used $$\T=300\,\text{K}\$$, which gives me a thermal noise (per FFT bin) of $$\P=-141\,\text{dBm}\$$.

The next 3 components in the receiver are an LNA, an RF amplifier and a mixer, which have reported noise figure (NF) and gains (G) of (all in dB):

LNA: NF=1, G=13

RF amp: NF=5.5, G=12

mixer: NF=14, G=-3

This gives me a cumulative NF of 1.7dB. I believe all of this is correct so far. Here's where it gets a bit trickier though. All inputs and outputs prior to the mixer output were matched to $$\50\,\Omega\$$. The mixer output has a differential impedance of $$\200\,\Omega\$$ and the IF amplifier that follows it has a high input impedance, and low output impedance as would be expected. The mixer output is AC-coupled to the IF amplifier input. So, I believe the next step is to take the cumulative noise power so far (at the mixer output), which is $$\-139.3\,\text{dBm}\$$ ($$\1.17\times 10^{-17}\,\text{W}\$$) and convert it to a voltage noise. $$\V=\sqrt{PR}\$$, which gives me a voltage of $$\48.5\,\text{nV}\$$ ($$\R=200\,\Omega\$$).

The IF amplifier datasheet contains a section detailing how to estimate the output noise voltage. I've followed these instructions (and checked it against their calculator mentioned in the datasheet) and got a output differential voltage noise density of $$\90.8\,\text{nV}/\sqrt{\text{Hz}}\$$. I multiply this by the square root of my FFT bin bandwidth (stated earlier) to get about $$\4\,\text{\muV}\$$ of noise voltage added by the IF amp. Then I apply the gain to the mixer output voltage noise (48.5nV) and add that to the $$\4\,\text{\muV}\$$ I just found. $$\23.5\,\text{dB}\$$ as a linear voltage gain is $$\15\$$, which amplifies the mixer output noise to about $$\0.7\,\text{\muV}\$$. Add that to the 4 gives me $$\5\,\text{\muV}\$$ thermal noise at the ADC input. I'm slightly less certain about this 2nd part, but I still feel everything is correct. Now here's where I'm stuck. Normally I'd convert this back to a power level using the ADC input resistance. However, it doesn't appear that the ADC I'm using listed the analog input resistance anywhere. At least I can't find it in the datasheet. Is this typical? How can I convert this back to a power level? Do I assume a differential input impedance? For instance, if I were to use $$\1\,\text{M\Omega}\$$, I would have a noise power of $$\-136\,\text{dBm}\$$. I guess this seems reasonable, but assuming the ADC input impedance doesn't feel very precise. Conversely, if I assume a larger input impedance at some point the noise falls below the initial value of -141dBm. This, of course, can't be correct.

• As you are close, I will give you pointer first. Your ADC has a input S/H stage, so what you care about is the sampled noise power on the capacitor. This rather shockingly does not depend on the drive resistance rather only on its effective noise temperature. The datasheet tells you the S/H capacitor size and you can take it from there. – Adil Malik Feb 13 at 22:37

Excllent realworld design challenge. [ see end of my answer for discussion of the ADC datasheet ]

The ADC has numerous internal random thermal Boltzmann noise generators. And one LARGE correlated variance generator --- the quantization error, which may dominate. And those circuits have finite Power Supply Rejection of trash, so you need to FILTER the VDD pins.

At least ONE noise generator is costly in area and INPUT SIGNAL POWER. Other noise generators are costly in VDD POWER and in glitching of the internal VDD rails. Thus lowering the "noise floor" of an ADC is a balancing_act.

(A) The input sampling cap (probably 10pF or less), using

• V_cap_noise = sqrt(K & T / C) is exactly 20 microVolts_RMS for 10pF.

Larger sample_hold caps require more signal noise. At 100MHz Fsample and 10pF and 1volt charging transient, the power is P = F * C * V^2

The power DEMANDED FROM SIGNAL SOURCE is 100MHz * 10pF * 1^2 = 1 milliWatts.

Charging that 10pF (may be smaller, for really fast ADCs) must be done with cleanly settling action. Some companies sell SiliconGermanium opamps for this.

Realize the (computed) value of 20uVrms is total integrated noise, spread over the Nyquist bandwidth of the ADC. Does that mean "DC to Fsample/2" ??? You must decide that.

(B) The comparators that make the binary approximation decisions will have noise in their bipolar or FET transistors. For bipolars, the dominant factor is the rbb' where the input base signal enters the useful region between emitter and collector. For FETs, the standard model for noise is dominated by 1/gm of the FET channel at the operating point (which in transient/decision making will vary wildly); if the FETs have poor layout on silicon, there can be gate_charge movement noise generation, but that noise contribution has been known for decades and should be in the maths.

To predict the comparator noise, use 10GHz noise bandwidth (allows 16 picosecond * 2 for the positive_feedback decision loop, exiting metastability). And assume high current (several milliAmps) to produce transconductance of 1/1K ohm, thus Rnoise is about 1Kohm, promising 4 nanoVOlts/rtHz noise density.

The total comparator noise is swqrt(10GHz) * 4 nanoColts.

Or sqrt(10^10) * 4 nanoVolts = 1e+5 * 4e-9 = 4e-4 = 400 microVolts RMS.

Thus the comparator noise should dominate.

But what is your Quantization Noise? I think its Vquanta/sqrt(12).

A 1 millivolt quant gives 0.001/3.5 or 0.28 milliVolts CORRELATED noise.

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The datasheet tries to be helpful in this system design.

The full power bandwidth is 575 MHz.

The transition noise is 0.25 Quanta RMS.

The SNR varies slightly with sampling frequency, but is 71dB +-1 dB.

Also read page 23, regarding PhaseNoise.

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The ADC will have a sample_hold input capacitor + FETswitch + optional lumpedResistor.

All of that is just a low Pass Filter responding to VOLTAGE.

• Thanks for the detailed response! This seems to focus on estimating the noise contribution of the ADC. However, I'm fairly content accepting the datasheet value of $71\pm1\,\text{dB}$. What I'm really interested in is the power noise right before the ADC starts contributing noise. – MattHusz Aug 1 '20 at 17:14