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A previous iteration of my circuit was as follows:

  • I am sensing DC voltages across 6 variable resistors (1kΩ Pt RTDs)
  • The 6 resistors are connected in series; the series is connected to a current source (LM334 set to 0.28mA) on the high side and ground on the low side (this both provides bias current return path and limits current through each RTD to <0.3mA as required by their spec)
  • Each resistor has Kelvin connections to a 12-bit 12-channel track+hold ADC (MAX11617) configured in differential mode
  • Some I2C stuff to get data out of the ADC

After prototyping this, I found the ADC readings to be very noisy, which I eventually realized was due to the ADC inputs having a high-impedance (GΩ range, due to the current source), leading to slow charging of the internal track+hold capacitor in the ADC as well as crosstalk between ADC channels, and resulting in signal degradation. I confirmed this by first ensuring that the ADC inputs were stable (they were, with ≤5mV peak-to-peak variation, which is mostly attributable to power supply noise in the prototyping setup) and then bypassing each ADC input to ground a with 0.1µF ceramic capacitor. The output signals immediately stabilized with bypassing.

The time constant of the resulting RC network on the ADC input was in the ballpark of 10s, which may be okay for my application. However, the MAX11617 data sheet recommends buffering the inputs in this case, so I decided to explore that.

In the current iteration of the circuit:

  • The series configuration of the sensors and the current source is retained.
  • The Kelvin connections from RTDs are now going to instrumentation amplifiers (INA2332, configured with gain of 5 and 0V reference voltage).
  • The 6 outputs of the instrumentation amplifiers are going to 6 inputs on the same ADC, now configured in single-ended mode.
  • I2C stuff is retained

However — and this is where I am baffled — this also resulted in noisy ADC readings. I again confirmed that ADC inputs (aka amplifier outputs) are stable (≤5mV P2P variation) and then again tried bypassing the ADC inputs to ground with 0.1µF MLCCs. The outputs stabilized with bypassing.

This suggests I am seeing slow T+H charging times again, but now I am confused as to why that is happening; my understanding was that the whole point of using an instrumentation amplifier was that it has a low impedance output, and so I was expecting the ADC outputs to be stable when multiplexing across 6 low-impedance inputs.

Thoughts?

PS: Tried making a minimal working example with only 2 RTDs and can't repro the problem. I will rebuild the original example one step at a time until the problem reappears, and I'll be back when I have more info from that.

Schematic of current iteration:

enter image description here

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    \$\begingroup\$ ADC inputs will not be high impedance- the RTDs will dominate the resistance, so ~ 600\$\Omega\$ maximum for 100 ohm RTDs, not G\$\Omega\$. Please supply a schematic. Connecting capacitors directly to an in-amp output is generally not a good thing to do. \$\endgroup\$ – Spehro Pefhany Aug 2 at 19:19
  • \$\begingroup\$ @JRE Added schematic of current iteration. Don't have a readily available schematic of previous iteration, but probably doesn't matter since the question is why am I seeing noisy outputs in the current iteration. \$\endgroup\$ – Ben Artin Aug 2 at 20:13
  • \$\begingroup\$ What is the acquisition time, typical voltage across each RTD, noise and crosstalk with direct connection and with instrumentation amps? Can you show us the physical layout (PCB and/or photo of setup)? \$\endgroup\$ – Bruce Abbott Aug 2 at 20:34
  • \$\begingroup\$ @BruceAbbott I am testing @ room temp with 1kΩ RTDs and 0.28mA current set by the current source, so typical voltage across each RTD is ~0.28V. I am running MAX11617 in internal clock mode, in which conversion time is ≤7.5µs. Input noise was ≤5mV P2P in both scenarios (as I mentioned, this is mostly attributable to the power supply the prototype is currently using). Noise in the ADC output signal was in the ballpark of 20-100 mV (if I recall correctly) in the direction connection and is in the ballpark of 200-300mV with inamps. \$\endgroup\$ – Ben Artin Aug 2 at 21:02
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    \$\begingroup\$ How bad is the breadboard prototype layout? Inexplicable noise on the outputs that you don't see at the inputs certainly could be a layout problem. \$\endgroup\$ – user1850479 Aug 2 at 22:24
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The problem was that the 1kΩ RTD-in-series setup was driving the common-mode input on several of the inamps out of their common mode input range, which resulted in noise on their outputs. That noise was then passed on to the ADC, where crosstalk coupled it into all ADC outputs.

My previous assessment that "ADC inputs were stable" was incomplete, in that I had unstable output on all ADC outputs, but checked input stability only on some ADC inputs. As it happened, I got unlucky and only checked ADC input stability on ADC channels coming from inamps that were being operated within their CM input range; those ADC inputs were, indeed, stable. Some others weren't.

This is also why the problem disappeared when I tried to repro with only 2 RTDs; inputs closer to 0V were within CM input range. I gradually built up from there and as soon as I stacked up enough RTDs, noise was coupled into all ADC outputs. Some additional isolation / part swapping ensued and I narrowed down the problem. I fixed it by breaking up the series arrangement of RTDs into two branches, thereby keeping CM inputs in the lower half of what they were before. With that setup, my noise on ADC outputs is 1-2mV P2P.

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  • \$\begingroup\$ What did you find the common mode range to be? \$\endgroup\$ – Bruce Abbott Aug 8 at 8:18
  • \$\begingroup\$ @BruceAbbott The data sheet for INA 332, if you stare at it hard enough, gives the CM input range to be from VREF / 5 to VDD - 1.2V, assuming gain of 5. My VREF = 0V and VDD = 3.3V, so my nominal CM input range is 0V - 2.1V, and that's not far off from what it appears to be in practice. \$\endgroup\$ – Ben Artin Aug 9 at 21:08
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Given the low impedance of the RTD, and the SLOW changes of temperature, the thought of Crosstalk as a major accuracy seems novel and reaching.

Given in your question, the addition of capacitors to ground has usually reduced the noise (the ADC output code spread), I'd think about reducing Gound Noise between the Sensors and the ADC Ground pins. Does a SWitchReg provide the power. How does the MCU get its power? What MCU outputs use the "ground" as return paths?

Can you show a photo of the prototype, and indicate where the numerous VDD bypass capacitors are GROUNDED. To a heavy, wide, ground.

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  • \$\begingroup\$ ADC crosstalk is not driven just by input signal frequency, it's also driven by the switching frequency of the mux that is internal to a multi-channel T+H ADC. This particular ADC samples one input per I2C clock cycle, and the system is running at 100kHz I2C clock. In other words, from the perspective of the internal ADC circuitry, it's digitizing a 100kHz signal (± I2C clock stretching, but that's the ballpark), and at that frequency, crosstalk is an entirely reasonable explanation. (Running out or else I'd link you to a technote that covers this.) \$\endgroup\$ – Ben Artin Aug 2 at 23:31
  • \$\begingroup\$ Also, I already said that noise on ADC input is ≤5mV P2P and ADC output noise is 100-400mV P2P, so noise filtering on ADC input is IMO not where the problem lies. I am not going to spend time adding input noise filter unless you can give me a convincing reason why adding more noise filtering to a signal that's already ≤5mV P2P is going to make a difference in the >100mV noise in ADC output. \$\endgroup\$ – Ben Artin Aug 2 at 23:34
  • \$\begingroup\$ ground noise was not the primary source of ADC output noise. Exceeding inamp CM input range was. Thanks for helping me think about where the problem might be coming from. \$\endgroup\$ – Ben Artin Aug 8 at 1:44
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We can't see your layout, so it's impossible to comment on how much, if any, it may be contributing.

I would suggest at least the following filter on each RTD input:

schematic

simulate this circuit – Schematic created using CircuitLab

All capacitors are NP0 ceramic types.

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  • \$\begingroup\$ I am not saying this is a bad idea, but I don't see how it answers my question. I ascertained that ADC input has minimal noise and ADC output has unacceptable noise; I don't see how input filtering is going to fix that, except for one thing: adding 100nF between ADC input and ground is going to help with (what I believe is) the issue of charging the internal T+H in the ADC. As it happens, I did try that; 100nF (which is the recommended value per MAX11617 data sheet) was insufficient to stabilize the output. (Beyond 100nF, the data sheet says to use a buffer, which is how I got here.) \$\endgroup\$ – Ben Artin Aug 2 at 22:19
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    \$\begingroup\$ Without the series resistors you're asking for trouble. \$\endgroup\$ – Spehro Pefhany Aug 2 at 22:34
  • \$\begingroup\$ Again, you aren't wrong, and you aren't answering my question. Those series resistors are not going to prevent the output noise my question is about, as far as I know; if I am wrong about this, I'd appreciate hearing why. \$\endgroup\$ – Ben Artin Aug 2 at 23:17
  • \$\begingroup\$ Without the series resistor, the input and output are the same node. Use appropriate filter layouts to filter. It is absolutely basic knowledge that a capacitive low pass filter exists out of a resistor and a capacitor, not just a capacitor. \$\endgroup\$ – LukeHappyValley Aug 3 at 11:45
  • \$\begingroup\$ Inamp input filtering was not the issue. Exceeding inamp CM input range was. Thanks for helping me think about where the problem might be coming from. \$\endgroup\$ – Ben Artin Aug 8 at 1:46

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