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If have designed the following circuit to convert a certain analog signal of an amplifier to digital pulses. The circuit works well - except for one point. enter image description here

My prototype PCB has 4 of these amplifiers and transistor circuits on it and when one transistor produces a pulse the others do as well.

I did many tests in the last week, an I isolated the problem to the shown transistor stage. So my guess is right now, that the fast rising collector current of the transistor, causes some short high frequency burst in ground, which is then picked up by the other amplifiers. however I am not able to fully measure this.

I added C2 (and tried different values, to smoothen the pulse flank) as an afterthought and this already improved it, but not for all situations.

So my next idea is, to separate the GND plane of the amplifiers from the transistor stage - this looks to be the best, as when I remove the transistor stage from the PCB, everything works fine.

But here is also where I struggle.

I plan to put the 2 planes together at a star point. Here is the layout without GND: enter image description here

As the emitter of the transistor is kind of on both GND planes and the star point is quite far from the transistor, I struggle on to which GND plane I should connect the emitter. I tend (just by feeling) to choose the 3V3 GND as this current is what causes the problem in the first place and as this current is much higher. However, I am worried, that the "small" current flowing through C1 in a pulse situation, has to go all up to the star ground point and back to the transistor, if I connect it like this.

So the 3 options are:

  • connect to 3V3 GND
  • connect to 15V GND
  • connect to both (but then I guess, I'm back to square 1 as this is already the original layout).

I hope, I described the problem clear enough, otherwise, please let me know in the comments, if need some more information.


Edit1:

The Original layout looks something like this: enter image description here The bottom layer is 1 solid GND fill.

Now I am thinking about something like this: enter image description here

Closeup of the transistor circuit: enter image description here

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    \$\begingroup\$ If you think the problem is ground bounce, then you need to show GND in the layout and also show how the channels are arranged relative to each other. \$\endgroup\$ – The Photon Aug 3 at 5:04
  • \$\begingroup\$ @ThePhoton I added some sketches for further explanation \$\endgroup\$ – KarlKarlsom Aug 3 at 6:12
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Well, you don't show how the grounds of the transistor and capacitor C2 return to the reference point of the amplifier. In order for the return currents from each detector not to intercat, you need to return them separately to the reference point, or at least keep them separated until they join to a solid reference point.

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