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I was looking at the PCIE specification, and I don't understand the requirement for coupling capacitors. For 2.5GT/s, the standard requires AC coupling capacitors of 75nF to 265nF. I tried to analyze the number like in this article in High-Speed Digital Design Online Newsletter. The line is terminated at both ends, the capacitor faces 100Ω, the RC time constant is 7.5µs to 26.5µs, or 19000 to 66000 bit intervals. Since we're using 8b/10b encoding and there are at most 3 ones or zeros in a row, the RC time constant only needs to be large compared with 3 bit intervals, so the capacitance should only need to be large compared with 12pF. The requirement of at least 75nF seems unnecessarily large. Why is that? If the capacitance were allowed to be around 100pF, the capacitors can even be made into the chip.

The requirement for coupling capacitors can be found here, page 357, section 4.3.13.

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The larger AC coupling value passes the low-speed 'ping' pulses used for sensing the presence of a link partner. The TX PHY sends the pulses, then watches the signal using the known R-C time constant to detect an open or terminated line.

Here's an excerpt from an article describing this:

"Receiver detection: PCIe uses an ingenious means to recognize both the presence of a physical link and channel width. The specification exploits the fact that an un-terminated, ac-coupled transmission line will have a very different charge time when the line is terminated versus open. Each PCIe transmitter, at the commencement of linkup, produces a low-frequency “ping” on each of the differential TX outputs. The transmitter includes a simple detection circuit to monitor the line response to this ping. With no receiver attached, the edge rate (and amplitude) of the line change is much higher than when a receiver is present. Because the specification has a defined range of coupling capacitance and the receiver termination, a distinct, detectable time constant range defines when a receiver is present or not."

From here: https://www.electronicdesign.com/technologies/communications/article/21762833/pci-express-and-the-physical-journey-to-gen-3

Once the link partners have found their connections, then the 8b/10b linkup and training process begins.

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    \$\begingroup\$ After I read the link, I went to the specification and found section 4.3.5 "Low Frequency and Miscellaneous Signaling Requirements" that explains all this. The spec is so long that I didn't know where to look before seeing your answer. Thank you. It looks like there is also the wake-up beacon that allows 32µs for DC level to be restored. \$\endgroup\$ – 7efkvNEq Aug 4 at 2:59

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