Is there a way that is not too complex way to implement ADC -> SRAM -> DAC data transmission without the usage of the microcontroller?

The application is to implement the audio loop of some sort, to put the audio input chunk to the memory, with an ability to stop the "ADC -> SRAM" process, to keep previously acquired data in the memory.

It does not have to be a high fidelity (I have 8-bit ADC/DAC in mind).

UPD: I want to do this for the educational purposes, so I'm not looking for the all-rational/optimal solution.

  • 2
    \$\begingroup\$ It depends what you might regard as complex. I built one back in the 80s that could slow down and speed up what was stored in memory and it didn't use a micro. \$\endgroup\$
    – Andy aka
    Aug 4, 2020 at 16:17
  • \$\begingroup\$ Sounds like a DMA controller \$\endgroup\$
    – Aaron
    Aug 4, 2020 at 16:18
  • 1
    \$\begingroup\$ Choose an ADC, choose a DAC, choose some memory and provide data sheet links. \$\endgroup\$
    – Andy aka
    Aug 4, 2020 at 16:22
  • 2
    \$\begingroup\$ You'll be building a small state machine (possibly just one FF) which alternately selects a read address (via a 2:1 MUX) and a write address to SRAM, and generates the read and write strobes. Every second cycle it increments a READ address counter, and (unless you have pressed the STOP button) also a WRITE address counter. About a dozen TTL chips in all, depending on the length of the counters. Use ADC and DAC with parallel I/O. (yes an MCU is much simpler) \$\endgroup\$
    – user16324
    Aug 4, 2020 at 16:43
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    \$\begingroup\$ You can do it all with a cheap CPLD. If you don't know HDL design though, there's a learning curve there similar to that with microcontrollers. The timing will be easier to make predictable than a microcontroller but that may not have been an obstacle anyway. If you want it simple, the CPLD logic design can derive control signals and addresses all off of one long counter. As ever, though, it depends what you're trying to do and what your priorities are. \$\endgroup\$
    – TonyM
    Aug 11, 2020 at 20:57

1 Answer 1


Yes, it is possible to do something like this. I saw a design from the 80's that used a ROM (27C64) and a 74HC4040 counter to generate a sine wave. The CD4017 counter also had one of it's upper address lines routed to an ADC that caused the ADC to sample and spit out a serial stream.

You could conceivably get an old ADC with a parallel output and use a counter to poll it and activate the WR lines of a parallel RAM, and then use a few flip flops to read the value back (I assume it's a delay you might be after)

But instead of building a physical system with 74HC series logic, the better way is to use an FPGA between the ADC and the DAC, especially if you don't need that much RAM, it would be much easier and more configurable.


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