I have a question about this piece of verilog code:
reg [31:0]ain = 3; reg aout = 0; reg bout = 0; always @(posedge clk)// A begin if (ain == 3) begin aout = ~aout; end end always @(posedge clk)// B begin if (aout == 0) begin bout = ~bout; end end
Basically this has 2
always@(posedge clk) blocks(
b) where the second uses a variable set in the first. Now assume this entire thing isn't optimized away and ain could have more values maybe.
I'm wondering what version or time of aout block B would use, since both blocks run at the same time. Would it be undefined behavior as A and B run at the same time? Or will B always use the value of aout that was set by A previous clock cycle? Or would it completely depend on whether A can complete before B?
The reason I want to know is because I want to create a riscv cpu where the instruction fetch and decoder and such are separated(instead of all combined like I have now) so that I can have it execute more instructions per second.
Also, what would be the best approach if I wanted to make sure B used the aout of A in the previous cycle?(So the result A set aout to at the end of previous clk)
Edit: It appears my question might be a bit vague so I will try and clarify. Currently my understanding(which I think is correct) is that A and B will be executed at the same time(in parallel), meaning that aout will change during the execution of A. However, B is trying to use the aout register for it's own logic. So my question is, will aout change value before or after it is used in the if by B? Or does it depend on whether the A block finishes before the if in block B? I need to know this so I can make sure that when I have more variables that I wont try to use the output from a half executed block.