Basic MOSFET small signal model with no load and Rd

I've come across the most basic small signal model of the MOSFET. We have a NMOS whose drain is connected to Vdd= 5V and source is grounded. We also have biased gate with a DC 2V. Suppose the condition for saturation is met.

Now what my confusion is when we hook up a small signal voltage to the gate of NMOS, 0.01vpp sine(or any small signal to considerably affect the output swing), the output would be vds= -gm* ro*vgs (all are small signal voltages). So basically our Vout= Vds must be swinging(let's say 4V-6V) with DC at 5V. But here, our Vdd(and hence the Vds) is fixed at 5V (with no AC) as provided by the supply.

Isn't it contradicting with the small-signal model? How is KVL satisfied? Also even if we assume that Vds is swinging(from 4V to 6V), is there any drop in the connecting wires to satisfy KVL? But I'm assuming the wires have 0 resistance and are very small to avoid any resistance.

• I am a little bit confused. You said the saturation is met with Vgs = 2V, so you should not expect any noticeable swing with so small the 0.01Vpp sine signal. I think perhaps you can try (1) not to go into the saturated region, and use a big signal (2). You may like to take 2N7000 to clarify your argument: (1)"2N7000 N-Channel Small Signal MOSFET 200 mAmps, 60 Volts, Rs(ON) 5Ω": onsemi.cn/pub/Collateral/2N7000-D.PDF. Cheers. Aug 5 '20 at 0:56
• But actually I am not too sure how to bias an Enhanced mode N-Type MOSFET in "A Class Mode" for amplification. Ref: "Enhancement-mode N-Channel MOSFET": electronics-tutorials.ws/transistor/tran_6.html. Aug 5 '20 at 1:06
• @tlfong01 we expect a very high gain(~10 dB) in saturation with a small change in vgs due to very large ro in our small-signal model. My question is not about gain. I need clarification regarding the contradiction that arose due to the small-signal model. Even if we expect Vout to swing even 0.1V at fixed 5V DC due to gain, it violates KVL. Aug 5 '20 at 1:28
• @MrityunjaySharma There's no violation. You have placed a voltage supply (taken to be ideal, but not really) across D and S. The variations placed at G (relative to S) merely adjust the current sink in the model. What's the problem you see with that? ($V_\text{DS}$ is fixed but the current varies a little.)
– jonk
Aug 5 '20 at 1:40
• @jonk I understand that Vds is fixed and the current varies a little. But what about the vds = -gm* ro* vgs, isn't vds supposed to change with varying vgs if we look into small-signal model as provided by theory? Aug 5 '20 at 1:52