I've come across the most basic small signal model of the MOSFET. We have a NMOS whose drain is connected to Vdd= 5V and source is grounded. We also have biased gate with a DC 2V. Suppose the condition for saturation is met.
Now what my confusion is when we hook up a small signal voltage to the gate of NMOS, 0.01vpp sine(or any small signal to considerably affect the output swing), the output would be vds= -gm* ro*vgs (all are small signal voltages). So basically our Vout= Vds must be swinging(let's say 4V-6V) with DC at 5V. But here, our Vdd(and hence the Vds) is fixed at 5V (with no AC) as provided by the supply.
Isn't it contradicting with the small-signal model? How is KVL satisfied? Also even if we assume that Vds is swinging(from 4V to 6V), is there any drop in the connecting wires to satisfy KVL? But I'm assuming the wires have 0 resistance and are very small to avoid any resistance.