I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into:
reg [7:0] k0, k1, k2, k3; reg [7:0] data1_tmp, data2_tmp; // Asynchronously read data from two registers always @(*) begin case (reg1) 0: data1_tmp = k0; 1: data1_tmp = k1; 2: data1_tmp = k2; 3: data1_tmp = k3; endcase case (reg2) 0: data2_tmp = k0; 1: data2_tmp = k1; 2: data2_tmp = k2; 3: data2_tmp = k3; endcase end
Logically I understand what it's doing. But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3. I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?
See I'm having a conceptual problem designing a simple verilog cache module. I have a data array containing all my tags like so:
reg [NUM_TAG_BITS-1:0] tag_array[NUM_BLOCKS-1:0]
And I have a wire "line_select" (from my input PC). What I want to do is retrieve tag_array[line_select] and then put it into a comparator with the tag from my PC to see if I have a hit.
But I thought whenever I access tag_array, I need to be inside "always @ (posedge clk)" code. Then I got stuck: how do I read from this tag_array and do the comparison all within the same clock cycle? So I found the above code online saying you can read from regs asynchronously, then I got confused because frankly I don't know enough about memory hardware and how that's possible.
Thanks a lot for any help!