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I am required to design an NMOS switch in UMC130nm process which is capable of enduring approximately 10V VDS (drain to source) when the gate is 0V. And a current of approximately 50mA when the gate is open (Vgs = 3.3V). Below are the transistor list in umc130 library to which I suppose none would be suitable for my application. enter image description here

My question is, given the spec above, is there any way to make a custom layout of such transistor (no matter how irregular it would be) without having them placed automatically by Cadence or would it be too far fetched? Below is a graph of a DC sweep on a single N_12_HSL130E nmos transistor. enter image description here It seems when Vds = 10, given Vgs = 0, approximately 40mA current passes through the transistor which I think is an indication of a catastrophe if manufactured right? I also don't have access to the process documentation, there could be hints regarding this issue. So any help is very appreciable at this point.

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To handle "high currents", you will need numerous (10+ contacts at source and drain and at any metal_to_metal layer changes.

There may be special rules about enlarging the wells around the active/source/drain regions.

And control signals (to the Gate) may be constrained in how they overlap active regions.

These rules will be in the Layout Manual.

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