I am required to design an NMOS switch in UMC130nm process which is capable of enduring approximately 10V VDS (drain to source) when the gate is 0V. And a current of approximately 50mA when the gate is open (Vgs = 3.3V). Below are the transistor list in umc130 library to which I suppose none would be suitable for my application.

My question is, given the spec above, is there any way to make a custom layout of such transistor (no matter how irregular it would be) without having them placed automatically by Cadence or would it be too far fetched? Below is a graph of a DC sweep on a single N_12_HSL130E nmos transistor. It seems when Vds = 10, given Vgs = 0, approximately 40mA current passes through the transistor which I think is an indication of a catastrophe if manufactured right? I also don't have access to the process documentation, there could be hints regarding this issue. So any help is very appreciable at this point.