So... I'm designing a kind of retro CPU testbed (Z80, 6502...), akin to a generic programmer such as the xgecu. I have an Atmega2560 as my microcontroller, and a 40 pin ZIF socket. All ZIF pins are redirected to known I/O MCU pins. I'll then have a configurable REPL working via Serial/USB.

My problem is on VCC/GND configuration. Not all CPUs have the same VCC/GND layout, and I'm not confortable with the Atmega2560 source/sinking the necessary current through its IO pins (although current CMOS versions of these CPUs do have very little consumption).

Besides a rail of 160 jumpers (to select VCC/GND for each possible pin), or an array of 80 transistors, what would be the most elegant way of arbitrary routing source/sinking paths in a programmable fashion?

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    \$\begingroup\$ I don't think there's any good approach to this. Designing PCBs for "everything" is a huge pain in the ass for a reason. Would daughter boards specific to the MCU, upon which the ZIF socket rides be out of the question? The daughterboard itself could carry the jumper slots you "probably" need (determined after looking at a bunch of MCUs and seeing which Vdd/Vss pins are most common) and you could solder the jumpers specific to the MCU. And if it turns out you run into an MCU that uses some pins that aren't accounted for, you just need a new daughterboard, not a new testbed. \$\endgroup\$
    – DKNguyen
    Aug 6, 2020 at 18:05
  • \$\begingroup\$ Dauhter boards, kinda, yeah :-/ I would most likely go through the 3 rows of 40 jumper pins. Altough you raise some interesting points. \$\endgroup\$ Aug 6, 2020 at 18:08

1 Answer 1


You could use two pieces 20x3 2.54mm pitch headers (120 pins total but only two parts to stuff) and one shunt for each power pin. Samtek ones are in stock at Mouser. Just run the GND and Vdd along the outside connections and link each center pin to a pin on the ZIF.

But I think I like @DkNguyen's daughterboard approach better. Less likely to fry a chip, for one thing.


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