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I have a circuit to demodulate 2KHz Infrared pulsed light which is generated by 555 timer IC and its output drives an IR transmitter circuit, which is received by IR receiver located 10 cm apart which amplify the signal with a transistor and then the output signal from it goes to missing pulse detector circuit based on 555 IC. Because I need a high pulse when an object block the IR light path between transmitter and receiver, I have used Schmitt trigger Hex inverter to invert the signal after the missing pulse detector circuit. Please see the attached schematic. IR Detector with missing pulse detector

This circuit works well except on the power on and power off conditions, where there are unwanted pulses on both the instances without any object blocking the iR light path. I am trying to find a way to avoid or remove those pulses without losing out the circuit above-mentioned ability. I have tried LM393 based comparator but it didn't help. I also tried RC filter to replace 555 missing pulse circuit but it only detect bigger object and does not solve the problem.

The unwanted pulses on power on and power off looks like as in screenshot below.

Unwanted pulse at power on and power off

The zoom in of power on unwanted pulse is, Power on Pulse

And the power off unwanted pulses in zoom in looks like, Power off unwanted pulse

What modification can I do to avoid these unwanted pulses? Or should I try a different circuit altogether?

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  • \$\begingroup\$ What does the collector of Q1 look like during the power up/down events? What does the 5V power look like during the power up/down events? \$\endgroup\$ – Aaron Aug 7 '20 at 0:07
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    \$\begingroup\$ is there any reason to keep the transmit and receive electronics separate? \$\endgroup\$ – jsotola Aug 7 '20 at 0:27
  • \$\begingroup\$ @Aaron : Output from Q1 at power up takes approx. 2.3 ms and power down take approx 200 ms. 5V rails power up takes approx. 2.3 ms and power down takes approx. 500 ms. \$\endgroup\$ – Nitin Kumar Aug 7 '20 at 2:07
  • \$\begingroup\$ @jsotola: they are not separate in this case, both share same power supply but you can also separate them if you like. \$\endgroup\$ – Nitin Kumar Aug 7 '20 at 2:10
  • \$\begingroup\$ @NitinKumar, no the two sides should not be separate unless necessary ... you could feed a transmit clock signal into the transmitter ... and feed the transmit clock signal and the received signal into an XOR gate ... the transmit clock signal and the received signal should be almost the same when nothing is blocking the sensor ... the XOR gate output would highlight the difference between the two \$\endgroup\$ – jsotola Aug 7 '20 at 5:53
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Take advantage of the reset pin to delay turn-ON time until Vcc is stable. It is the initial rising of Vcc 5 volts that causes glitches. With the values shown there is a turn-on delay of about 100 ms. The diode discharges C1 instantly so a quick power-up is still delayed.

Also, use CMOS TLC555 which does not have giant glitches at the outputs when changing states. Each 555 must have a 100 nF decoupling capacitor across its power and GND pins.

NOTE: Because the output is inverted, so are the problems. Remove any time delay at the 555 and use it to delay the output going high by using a AND gate and spare inverter gates. This way only the final output signal is blocked until glitches settle down. I understand why you had to invert the output, so it is best to block it until power is stable.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Should i try this on pulse generation 555 IC or missing pulse detector circuit 555 IC or both? My guess is missing pulse detector 555 IC. \$\endgroup\$ – Nitin Kumar Aug 7 '20 at 2:12
  • \$\begingroup\$ At least the missing pulse detector, if it is turned on last. \$\endgroup\$ – user105652 Aug 7 '20 at 2:32
  • \$\begingroup\$ I just tried the modification on missing pulse detector, now the power on is one long pulse instead of many pulses,same envelope and it is 29 ms long. Power off pulse is same as before. \$\endgroup\$ – Nitin Kumar Aug 7 '20 at 2:40
  • \$\begingroup\$ @NitinKumar It occurred to me that inverting the output created a hidden problem, so it is best to block the output for 50 ms or so until power is stable. It should block power ON glitches and power OFF glitches. This is the only logical place to fix the problem. Good luck. I added to my answer so please read it again. \$\endgroup\$ – user105652 Aug 7 '20 at 5:06
  • \$\begingroup\$ I tested this circuit today. Because I did not have AND gate ic at hand, so I made AND gate using two 2N3904 Transistors with 10K resistors at each input and 1K from last emitter to ground, I found several circuit on internet with same value so I made this one. Now, power on is reduced to under 400mV, though occasionally I still get around 1V to 5V pulse (1 in 20 times or so). Power down pulse is still there, though instead of 4.2V, it has reduced to 3.3V. \$\endgroup\$ – Nitin Kumar Aug 9 '20 at 16:43

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