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With reference to my previously asked question What stage is used to shift out TDO in JTAG? I have another querry.

The JTAG document says that the last bit of data/instruction should be shifted out the same time as Exit1 State is activated. However it also states that TDO is tri-stated in all the states except Shift-IR and Shift-DR states i.e just when Exit1 state is activated, in the following negetive edge of clock, TDO is tri-stated. That means the last bit information sampled on TDI in Exit1 state is lost! How to deal with this situation? I have simulated the RTl for JTAG and sharing the simulation results (waveform snapshot). Please guide.

Simulation JTAG

As seen in waveform, thr IDCODE register is shifted out with value 0xc3631093 and last 2 bits i.e 1 and 1 is shifted out on IDCODE_shift_out at 48.50 us and next 49.50 us respectively.

However TDO only captures the first 1 at 49.0 us and the next 1 is not captured as TDO becomes Z. The test sequence is such that I am shifting out IDCODE on TDO through the state Shift DR -- Exit 1 DR -- Update DR -- Run Test Idle and so on.

Just for reference, these are the different states coded

parameter TEST_LOGIC_RESET=0,
                RUN_TEST_IDLE=1,
                SELECT_DR=2, 
                SELECT_IR=3, 
                CAPTURE_IR=4,
                SHIFT_IR=5,
                EXIT1_IR=6,
                PAUSE_IR=7,
                EXIT2_IR=8,
                UPDATE_IR=9,
                CAPTURE_DR=10,
                SHIFT_DR=11,
                EXIT1_DR=12,
                PAUSE_DR=13,
                EXIT2_DR=14,
                UPDATE_DR=15;

Edit: Also adding the screenshots for IR selection and IDCODE Shift sequence. Please note, there is no Shift for IR, the sequence for IR is Capture-Exit1 IR-Update IR i.e Just write.

Waveform for IR selection - Selects IDCODE instrcution

Waveform for IDCODE shift

The first screenshot is for IR selection with timestamps

@12.5 us: Sel_IR is high in TAP controller

@13.5 us: Load_IR is high, IR value 0x001001 is pre-loaded

@14.5 us: Load IR register gets IR value (one cycle delay to capture). Meanwhile, Exit_IR state in TAP Controller.

@15.5 us: Update_IR is high, actual IR register updated(commited) with 0x001001

@16.5 us: Instruction sent to Decoder, decoder outputs 10 resulting in selection of IDCODE register. Sel_DR is high.

@18.5 us: Shift-DR is asserted, and IDCODE data is read into Shift register (Shift_idcode_q).

@19.0 us: Negedge of TCK, TDO gets LSB of shift data

@19.5 us: Data starts right shifting out from Shift register

Coming to waveform 2 screenshot

@49.5 us: MSB of IDCODE is shifted out. State is Exit-1 DR. Shift_DR is de-asserted.

@50.0 us: TDO is again tri-stated.

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  • \$\begingroup\$ Could you please add a screenshot of the full IR selection and shift sequence ? \$\endgroup\$
    – Nipo
    Aug 7 '20 at 7:25
  • \$\begingroup\$ @Nipo I have added the same. \$\endgroup\$
    – shaam
    Aug 7 '20 at 7:59
  • \$\begingroup\$ Thanks. Could you add the selection phase as well ? Just zoom out to have RTI state before and after. \$\endgroup\$
    – Nipo
    Aug 7 '20 at 9:55
  • \$\begingroup\$ You mean IR selection or IDCODE selection phase? I have already shared the IR selection phase. \$\endgroup\$
    – shaam
    Aug 7 '20 at 12:58
  • \$\begingroup\$ <xilinx.com/support/documentation/user_guides/ug380.pdf#page=171> Table 10.4 mentions (points 5,9 and 15) that if instruction is 6 bits, 5 bits are loaded in shift IR state and last bit is loaded in Exit 1 state when TMS = 1. \$\endgroup\$
    – shaam
    Aug 8 '20 at 3:50
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If I count correctly, your test bench is only spending 31 cycles in shift-dr. This is probably the cause for the missing bit.

On last Shift-* cycle, TMS=1, but current state is still Shift-*. Next state is Exit1-*. Overall, in order to shift N bits, JTAG chain must spend N cycles in Shift-*, among which N-1 cycles with TMS=0 and last one with TMS=1.

Here, you seem to spend N-2 cycles with TMS=0 and 1 with TMS=1.

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