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I am working with an LGA packaged IC. Each pad has a diameter of 0.5 mm and the distance between them is 0.3 mm. I need to pass tracks between those pads. According to the design rules, min (and preferred) track width is 0.1 mm, clearance of a pad is 0.05 mm and min distance between clearance and track is 0.1 mm. So, according to this, I cannot pass the tracks between two consecutive pads.

One thought of mine is to reduce the pad width by 0.1 mm in X-axis, giving it an oval shape, for the pads that I need to pass the tracks between them, like depicted below:

Design

In the picture above, K1, J1, G1, K2, J2 and G2 are the original pads, with a diameter of 0.5 mm and clearance (solder mask expansion) 0.05 mm, while H1 has been reduced to 0.4 mm on X-axis and H2 has been reduced to 0.4 mm diameter, for a demonstration.

Now the distance between the track and H1 and H2 is respected, and I am planning to do the same for the rest of the pads which I have to pass a track between them.

I have two questions on that:

  1. Will it have an impact on signal integrity? K1/K2, J1/J2, H1/H2, G1/G2 and the other pads are standard LVDS signals (1 is the negative, 2 is the positive)
  2. Should I reduce the size only in X-Axis, like H1, or both, like H2? I though that since only I have to pass a track between, then I could live Y-Axis to 0.5mm so it has more space for soldering.

Also, note that this will be only for the 20 something signal pads which I have to pass tracks between them, I will leave the rest 80 plus pads the correct size.

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  • \$\begingroup\$ What's wrong with routing on the opposite layer? \$\endgroup\$
    – Andy aka
    Aug 7, 2020 at 10:13
  • \$\begingroup\$ @Andyaka the tracks I want to pass through pads are actually signals from other pads of the same IC. For example I want to route K2, G2, J2 and many others, so I have to go through the other pads. Routing on the opposite layer in that case means I must place VIAs between pads or VIA-in-pads, which is not a cost effective option (at least in this time). \$\endgroup\$
    – Mr.Y
    Aug 7, 2020 at 12:43
  • \$\begingroup\$ Did you create the footprint with the IPC-compliant footprint generator? \$\endgroup\$ Aug 7, 2020 at 17:47
  • \$\begingroup\$ @SpehroPefhany no, I created it manually based on the package description provided in the datasheet. \$\endgroup\$
    – Mr.Y
    Aug 7, 2020 at 21:05

1 Answer 1

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Think about the reasons why the soldermask (and its related clearance) is used or regulated...

Besides the question/comment from @Andy aka , I'd say that for a limit situation like this one, there's no a "tight and rigid need" for having a soldermask clearance around solder pads (really there is, but this is a common trade-off problem!).

Having said that, on the contrary, the pad dimensions are very critical (due to solder joint reliability reasons), so that even if there could be more than one solution to the problem, maybe the simplest one could be leaving the original pad dimension and do not have a soldermask clearance at all, that is, making the soldermask apertures equals to the pads for that component.

By using this trick :

  • the design rules for pad-track isolation distances are respected
  • the track-pad isolation distance is preserved
  • due to unavoidable solder mask misalignment, the pad surface available for the solderjoint is almost preserved (I'd expect some further question about this point) -there will be no more problems about clearance-track distance

At any rate, please, take care that this solution does not exempt you from requiring to the pcb manufacturer to respect the "standard" max permissible soldermask misalignment valid for fine-pitch boards.

Edit

I did not notice that effectively 0.5 mm is an excessive pad diameter. If the LGA pitch is 0.8 mm, you can scale down to 0.4 mm for the pad diameter, solving all your problems; but, please, do not use oval pad because this will create uneven mechanical stress on solderjoints.

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  • \$\begingroup\$ Thank you for your answer, unfortunately after consideration and some discussions, avoiding the soldermask clearance is not viable (mainly because this is an on/off request by the manufacturer - either all pads will have or none, and we have many other ICs and components beside this one). \$\endgroup\$
    – Mr.Y
    Aug 7, 2020 at 14:38
  • \$\begingroup\$ @Mr.Y While I perfectly know and understand the reasons about the on/off requirements from pcb manufacturer, you should convince him that you could accept a limited (up to 50 micron) soldermask-on-pad overlapping. Anyway, please, read my last edited answer above. \$\endgroup\$
    – barrow
    Aug 7, 2020 at 15:17
  • \$\begingroup\$ You mean like I have done in the H2 pad, right? \$\endgroup\$
    – Mr.Y
    Aug 7, 2020 at 15:34
  • \$\begingroup\$ @Mr.Y Yeah!, you caught it. \$\endgroup\$
    – barrow
    Aug 7, 2020 at 15:54

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