# Calculate receiver dynamic range (understanding the effect of FFT processing gain)

I'm attempting calculate the dynamic range of a receiver. That is, the ratio between the maximum and minimum detectable powers at the reception antenna. The receiver is composed of (in order) an antenna, LNA, RF amplifier, mixer, filter and IF (differential) amplifier before being digitized by an ADC. The digitized signal then undergoes signal processing including an FFT. Most of this process I believe is straightforward. For instance, to calculate the maximum reception power I find the maximum ADC input voltage ($$\\pm 1\,\text{V}\$$ in my case) and work back using each stage's gain to find the corresponding signal power. Here's a plot of that to make this question a bit more concrete (the frequency-dependence comes from the filter).

Now I need to determine the minimum detectable power. As I see it, there are 2 things to consider here: (1) the receiver noise floor and (2) the limitation imposed by the LSB voltage of my ADC.

Let's start with #2. My ADC (LTC2292) has a precision of 12 bits and a peak-to-peak voltage range of $$\2\,\text{V}\$$. This gives it an LSB voltage of about $$\488\,\mu\text{V}\$$. I can use the same process I used for the maximum power to arrive at the minimum power this imposes. Here's the plot for that.

Now for #1. Through a lot of math (which I'm reasonably certain is correct) I found an RMS value for the voltage noise at the ADC (including the ADC noise) over the $$\20\,\text{MHz}\$$ bandwidth (this is the Nyquist rate since I sample the ADC at $$\40\,\text{MHz}\$$). However, the bin resolution of my FFT is $$\1.953\,\text{kHz}\$$. Therefore, the noise, which is uniformly distributed over the $$\20\,\text{MHz}\$$ bandwidth, is reduced by the bandpass nature of each FFT bin. So, the relevant noise voltage is the previous noise voltage I found divided by $$\\sqrt{10240}\$$. Now I can use the same process I've used twice before and convert this into an equivalent input power. This plot is shown below. I've also added an additional line to consider a minimum-detectable signal above the noise using a somewhat arbitrary value of $$\20\,\text{dB}\$$ (though I don't think the $$\20\,\text{dB}\$$ is really that relevant to this analysis).

Now, I believe the effective minimum power is the higher of these 2 contributions, which is of course the ADC resolution. So, my dynamic range would be determined by the difference (in dBm units) between the maximum power and the minimum power due to ADC resolution. This (unsurprisingly) is precisely equal to $$\20\log_{10}(2^{n-1})\$$ where $$\n=12\$$ is the number of ADC bits.

This answer feels wrong. In particular, it feels strange that the receiver noise floor is irrelevant because it is so far below the floor imposed by the bit resolution. I believe what I'm supposed to have done is applied the FFT processing gain equally to the minimum power imposed by the LSB resolution. The processing gain is $$\10\log_{10}(10240)=40\,\text{dB}\$$. If I decrease the minimum power imposed by the LSB resolution by this amount I get the following result.

In other words, the minimum power is imposed by the noise floor which is slightly above the limit imposed by the LSB voltage. The dynamic range then is the difference of the maximum power and the noise floor power, which is about $$\104\,\text{dB}\$$. However, I'm having trouble understanding how this can be correct (if indeed it is). In particular, how can I detect a signal weaker than the minimum-detectable $$\V_{\mathit{LSB}}=488\,\mu\text{V}\$$ imposed by the ADC? Is it that the FFT has a similar effect on $$\V_{\mathit{LSB}}\$$ as it did on the noise? In other words, the strength of this LSB voltage is shared over the FFT bins so that I also have to correct this LSB voltage by the same $$\1/\sqrt{10240}\$$ factor?

I'm adding a concrete example to illustrate my confusion. Imagine my signal is a perfect simple sinusoid with amplitude $$\100\,\mu\text{V}\$$ and frequency $$\1\,\text{kHz}\$$. When I run the same equations I've run to back out received power from ADC input voltage, I find that this corresponds to an input power of $$\-92\,\text{dBm}\$$. This is well above the minimum-detectable power I found by incorporating the FFT processing gain (that power at $$\1\,\text{kHz}\$$ was approximately $$\-115\,\text{dBm}\$$). So, my analysis would seem to suggest that my receiver is fully capable of detecting this $$\100\,\mu\text{V}\$$ signal. However, the ADC can't pickup anything less than $$\V_{\mathit{LSB}}=488\,\mu\text{V}\$$, so how could this be true? For instance, if my noise voltage were a constant $$\0\,\text{V}\$$, an ideal 12-bit ADC would output a constant $$\0\,\text{V}\$$ in response to this input. The only way I can imagine this signal can be detected is that when the noise is near the LSB rounding point, it will occasionally push the value to 1 LSB different than it would be if the signal were not there. However, I don't see how this translates into the clear signal detection implied by its SNR above the noise floor.

• The RMS noise in a perfect ADC is less than the quantization step. The dynamic range is normally quoted as 6.02N+1.76 dB. (N = number of bits). – Kevin White Aug 7 '20 at 20:23
• @KevinWhite, I'm aware of how to compute ideal SNR from quantization noise (this piece by Analog helped me with that, though bear in mind I'm using the datasheet SNR which incorporates more than just quantization noise). Anyway, if you read on in that paper the next part discusses FFT process gain. I think I understand how FFT process gain applies to noise too. However, my question is about how FFT process gain applies to the ADC LSB voltage. – MattHusz Aug 7 '20 at 20:30
• I think a source of confusion here (quite possibly on my part) is that I’ve used the LSB voltage in 2 different ways: as a source of quantization noise and separately as a minimum detectable value. – MattHusz Aug 7 '20 at 20:44
• I don't see how the system voltage dynamic range could ever exceed the ADC voltage dynamic range. (unless you have variable gain stages in front of the ADC). But I am not a signal processing guru. In other words, assuming all your gain stages are fixed, you cannot have two digital signals where one has a peak-to-peak amplitude greater than 2^n-1 and the other has an amplitude less than one ADC count. Even if you do have variable gain stages, you can never allow a signal amplitude to be greater than 2^n-1 because it will clip/saturate and pollute multiple frequency bins in the FFT result. – mkeith Aug 8 '20 at 0:21
• @mkeith this was essentially my question as well (to clarify, I do not have variable gain stages). It sounds like (and I may be wrong because I was only just introduced to this) even though the dynamic range of any one sample compared to any other can't exceed the ADC voltage dynamic range, the expectation value across multiple samples can. The uncorrelated nature of the dither with the signal is critical because it allows the expectation value to equal the actual value (see KevinWhite and user1850479's answers and associated comments). – MattHusz Aug 8 '20 at 0:43

In order to be able to convert signals below the quantization level, a dither signal such as a sawtooth must be added to the wanted signal. - Wikipedia - Dither.

A signal with suitable probability density should be used but thermal noise can be adequate. The added signal decorrelates the quantization noise from the signal so it just adds to the noise level across the entire spectrum.

• Is the general idea here that because the dither adds uncorrelated noise to the signal, the expectation value of the signal after several samples is equal to its value? To use @user1850479's words, because my $100\,\mu\text{V}$ signal spends 1/4 its time at 0 LSB=$0\,\mu\text{V}$ and 3/4 its time at 1 LSB=$400\,\mu\text{V}$, its expectation value will equal its value ($100\,\mu\text{V}$)? – MattHusz Aug 8 '20 at 0:34
• @MattHusz - yes, that's it. Over a number of samples it will average out. – Kevin White Aug 8 '20 at 0:46

[ fixed error Aug 8: final GAIN was only 70dB (error). Should be 90dB ]

Use the ADC RMS quantization noise (Vquanta / sqrt(12)) which is 488uV/ 3.5 , or

• ADC RMS floor = 140 microVolts RMS

Now let us take in a RF signal of 1MHz bandwidth, 50 ohm system, 0 dB noise figure, no close_in_blockers to worry about. And amplify until the in_band noise (that 1MHz bandwidth) is also 140 microVolts RMS.

The noise_density of 50 ohms is 0.9 nanoVolts per rootHertz. This dimension --- per rootHertz --- serves to remind us that the voltage increases as square root of the bandwidth. Using Power = Voltage^2 / Resistance, we can also see the Power increases linearly with bandwidth.

Our 1MHz bandwidth, square rooted, gives a factor of 1,000X to apply to the 0.9 nanoVolts per rootHertz. The "per rootHertz" dimension also is canceled, and we end up with, out of the antenna, the input random noise we need to know:

• Noise Input Voltage, in 1MHz Bandwidth, is 0.9nV * 1,000 = 0.9 microVolts.

We now might decide to have the signal_processing front end, from LNA to IF amplifier, contribute the same amount of noise as the ADC. That would require gain of

• 140uVrms / 0.9uVrms == `150X, or about 43 dB [had been 23 dB]

However, this ignores the BINNING power of the FFT. What to do?

The QUESTION suggests a desirable minimum Signal_Noise_Ratio SNR of 20dB within a bin.

If we let the ADC set the SNR, we need 4+ bits of resolution, thus the Vin to the ADC needs to be at least 16 Vquanta, or about 8 milliVolts (ignoring peak, peakpeak, rms questions here).

In a 1KHz bandwidth (the ADC bin spectral width), which implies 1,000 conversions per second, and thus a muddying of modulations faster than 1KHz, the Input Noise Density of 0.9 nanoVolts per rootHertz becomes sqrt(1,000) bigger, or

• Input Random Noise in FFT bin = 0.9nV * 31.6 == 28 nanoVolts.

Given 28 nanoVolts random noise, we need 20dB stronger RF input, which is

• RF input level = 28 nanoV * 10 == 280 nanoVolts RMS

We can now compute the MATCHING/LNA/RF/MIXER/IF GAIN needed, as

• Gain = 8 milliVolts / 280 nanoVolts

• Gain = 8,000 uV / 0.28 uV == 30,000X or 90dB [ had been 70 dB]

Now you decide how to compute the front end gain.

In particular, how can I detect a signal weaker than the minimum-detectable VLSB=488μV imposed by the ADC?

Your SNR is limited by your quantization noise power, not your quantization step size. These are very different things. If your signal bandwidth is small, you can detect signals much smaller than the step size because your quantization noise is approximately uniform with frequency while your signal is not.

• I'm still confused. Imagine a scenario in which my signal is a perfect simple sinusoid (i.e. single frequency) with amplitude $100\mu\text{V}$. No size FFT (equivalently, decrease in bandwidth) is going to allow me to detect this because it isn't large enough to register as at least 1LSB, even though it allows me to arbitrarily decrease the noise. What am I missing/doing wrong here? – MattHusz Aug 7 '20 at 22:29
• Detection of signals much less than 1 LSB is both possible and common. Your phone does this constantly, as does any 1 bit sigma delta ADC. There is nothing special about the quantization step size. – user1850479 Aug 7 '20 at 22:50
• I've incorporate this comment into my original question with specific, realistic numbers. If this is indeed possible, can you explain in the context of that example? – MattHusz Aug 7 '20 at 22:51
• If your amplitude is 1/4 your step size, you'll spend 3/4 of your time at one level and 1/4 at the other. The frequency at which you switch between them will be the frequency of your sinusoid. Note that there are ADCs out there where this will not work (see all those assumptions that go into derviving 6.02N+1.76 dB), but those are uncommon. – user1850479 Aug 7 '20 at 23:46
• Is this due to the effect of dither, as mentioned in another answer? – MattHusz Aug 8 '20 at 0:11