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As the subject indicates: can I use different voltages for the different IO banks? (1.8V for some, 3.3V for some others)

Neither the datasheet nor the hardware checklist technical note explicitly say, AFAICS.

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    \$\begingroup\$ Can you share a link to the datasheet? Normally that's the whole reason to define banks --- so you know which IO pins need to be grouped together on the same supply voltage. \$\endgroup\$
    – The Photon
    Commented Aug 8, 2020 at 0:00
  • \$\begingroup\$ @ThePhoton ‒ Edited the post. "Normally that's the whole reason to define banks". That's my intuition too. But then, I though a secondary and also important reason was the possibility to save power by not supplying power to banks that are unused. And yet, the Hw. chklist tech note explicitly states that all voltages must be supplied for the device to operate properly. So, that cast doubt about the intuition that separate banks could have independent supply voltages. \$\endgroup\$
    – Cal-linux
    Commented Aug 8, 2020 at 0:35

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The key document is one you didn't link to, but which is linked from the datasheet, the Lattice XP2 SysIO Usage Guide.

The most explicit indicator that the VCCIOs can have different values is on page 8-4:

enter image description here

There are further contextual cues that VCCIO's can be different for different banks:

  • The VCCJ supply voltage is explicitly described as being "independent of the bank VCCIO supplies". (note the plural)

  • It's explicitly mentioned that input pin voltage levels can be different in a bank (under the heading "mixed voltage support in a bank").

To be sure, you could create a simple design that uses differently-supplied output pins in different banks, and one that uses differently-supplied output pins in the same bank. The place and route tool should give an error for the second case but not the first.

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  • \$\begingroup\$ At the risk of sounding dense, I will say that I had seen this comment in this document; the problem I see is that, strictly speaking, that tells me that banks have their own supply pins; but it does not (explicitly) say that the actual voltage of each bank can vary independently of the others. Maybe I'm mistaken on that (linguistic subtlety, perhaps — English is not my first language); or maybe they simply thought that this possible alternative interpretation is so absurd that no-one in their sane mind could think that that's the case, so they didn't bother to say it explicitly? \$\endgroup\$
    – Cal-linux
    Commented Aug 8, 2020 at 1:12
  • \$\begingroup\$ @Cal-linux, I agree it could be stated more clearly. But see my last paragraph for how to find out for yourself. \$\endgroup\$
    – The Photon
    Commented Aug 8, 2020 at 1:13
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    \$\begingroup\$ If you go back to the first FPGA family that introduced IO banking, it will probably be said very clearly that the different banks can have different VCCIO. Since then (at least 20 years ago) the concept of IO banks has just become so fundamental that apparently they don't see the need to spell it out in newer documentation. \$\endgroup\$
    – The Photon
    Commented Aug 8, 2020 at 1:16
  • \$\begingroup\$ Oh yeah, I did notice your suggestion. I will have to dig through the Lattice Diamond help to figure out how to implement those aspects. \$\endgroup\$
    – Cal-linux
    Commented Aug 8, 2020 at 1:17
  • \$\begingroup\$ "... so fundamental that apparently they don't see the need to spell it out in newer documentation". I thought that might be the case, and since my experience with FPGAs only goes back a year or two, that would explain my "paranoid" feeling. Still, I kind of find it puzzling that this chip does not allow to omit VCCIO for unused banks (I seem to recall seeing that, explicitly stated, in Xilinx's Zynq documentation .... it might be my memory playing tricks, though). That seems to also go with the whole rationale behind I/O banks. And it sort of triggered my "paranoia" about the issue. \$\endgroup\$
    – Cal-linux
    Commented Aug 8, 2020 at 1:23

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