# Collector current in a BJT transistor whose base and emitter are forward biased

I'm reading a book about electronics and I have a doubt about a NAND gate implemented with Transistor-Transistor Logic. The question I have is actually about BJT transistors specifically (not the gate itself). I thought I understood how BJTs work, however, in my book, there is a new type of connection I don't understand very well, let me explain:

The NAND implementation the book provides is the following:

Now, my question is about Q1. Quoting the book:

[...] If both A and B are high, Q1 has no emitter current; however, its base-collector junction is forward biased, supplying base current to Q2. [...]

My understanding is that, if A and B are high, the voltage between them is 0, therefore the BJT is opened, so no current flows from its colletor to its emitter. However, the book states that the Q2 base receives current. That is what I don't understand.

Does this mean that the voltage in the Q1 base drives current to the Q2 base as well? If so, does this work the same way (but with voltages) with MOSFETs?

Here (BJT regions of operation), the BJT regions of operation can be seen. However, there is no region for B = E > C. What region of operation in the above table is supposed to describe this one?

Does this mean that the voltage in the Q1 base drives current to the Q2 base as well? If so, does this work the same way (but with voltages) with MOSFETs?

Don't know what you mean by Q1 voltage driving current to Q2 base. Q2's base current is common with current through Q1's base-collector diode junction, and through 4K pull-up as well. With no emitter current(s), Q1 is simply a base-to-collector forward-biased diode. The characteristic curves that might be included in a transistor data sheet don't address this biasing arrangement...more concerned with active-region transistor operation.

Logic threshold voltage for TTL is in the 1.2V to 1.3V ballpark. Consider the situation when A & B are logic high. Q2 is a bipolar switch that is saturated "ON". If you simplify transistor "ON" base-emitter voltage as 0.6V, then Q2 base is around +1.2V... because Q2 is switched "ON" and Q4 is saturated "ON" as well.

If Q2 base is 1.2V, so is Q1 collector. Q1 base is 0.6V higher, at 1.8V. If DC supply is +5V, then Q1 base current is $$\ (5-1.8)\over{4000}\$$ = 0.8mA. All this base current flows through 4k, and through Q1 base-emitter junction, into Q2 base. That's enough current to saturate Q2 fully "ON"...Q2 collector-to-emitter voltage clamps to a fraction of a volt. Q2 collector-to-emitter current is established by 1600 ohm resistor...around 2mA or a bit more.

Only when input A or input B falls below the 1.2V threshold does Q1 start acting as a transistor, when its base-emitter becomes forward biased. Q1 collector then pulls Q2's base toward ground, releasing it from its "ON" state, and pulling it out of saturation.

I suppose you could re-arrange a TTL input stage to use MOSfets. Getting MOSfet threshold voltage to be "TTL-compatible" would be a problem. MOSfets might pull Q2 base up, or allow "Rpulldown" to pull Q2 base down to ground to switch the NAND gate output to "high" state. Or MOSfets might replace Q1, Q2 entirely. A strange brew - not practical.

simulate this circuit – Schematic created using CircuitLab

By floating A and B, the base current can only go out the collector,

and

into the NPN with grounded emitter.

• but A and B aren't floating, they are both supposed to be at, say, 5V. Could you clarify that? How is that the Q1 base current can't go the other side, to Q2 and Q3 collectors? Aug 8 '20 at 14:45
• Even if A and B are connected to 5V, the base is connected to 5V via a resistor and its potential is slightly below 5V. So the current cannot flow in to either A or B since they are at a higher potential (5V). But the base current can come out of the collector of Q1 and flow into base of Q2.
– AJN
Aug 8 '20 at 15:25
• Where do you see the base is connected to 5V? Aug 8 '20 at 17:00

The base of Q1 will be at ~3 diode drops above ground (Q1 + Q2 + Q4), ie about 2V.

With the emitters at > 2.4V (TTL High) there will be some current flowing in from the emitters due to Q1's inverse beta. This is controlled by device processing to be small < 40uA worst case.

All of the base current plus the small emitter currents will flow into Q2.

When A and B are both held high Q1 is in reverse active mode. In this mode conventional current flows into the emitter and out of the collector. The disadvantage of this mode of operation is that the transistor's hFE is much smaller than when in forward active mode.