# Bypass cap on reference voltage?

For a voltage reference providing a reference to multiple devices, ADC, DAC, instrumentation amp... would there be some benefit in placing bypass caps right at the reference input to these devices even though they have high input impedance?

• depends on the device datasheet Aug 9, 2020 at 3:10
• Well, it depends on many things, including: (1) How accurate you want your applications, say, 8 bit or 24 bit resolution, and if you want as, or more accurate as possible. (2) How many pieces of equipment you are going to make, say 10 pieces, or 5,000. In short, it is an engineering trade off and cost benefit analysis of money, time, reliability, risk etc etc. Now let me come back to your question. (a) You already hinted that the equivalent total device input impedance at the voltage reference is "high", say all MOS of order 100M, then / to continue, ... Aug 9, 2020 at 3:48
• Then the by pass cap with a typical value of 10uF would source "negligible" current, and increasing its value to say, 100uF, won't make much difference in keeping the reference voltage source more stable, therefore the ADC/DAC etc more accurate, except wasting space. In other words, there is not much high frequency voltage spikes for the cap to filter or by pass. But then beside the "by passing" function, there is the cap's "decoupling" function to consider, / to continue, ... Aug 9, 2020 at 3:57
• To understand what is the meaning of "decoupling", I usually recommend to read the following two articles: (R1) "Clean Power for Every IC, Part 1: Understanding Bypass Capacitors - Robert Keim, 2105spe21": allaboutcircuits.com/technical-articles/…, (R2) "Clean Power for Every IC, Part 2: Choosing and Using Your Bypass Capacitors, Robert Keim, 2015sep27": allaboutcircuits.com/technical-articles/…. / to continue, ... Aug 9, 2020 at 4:09
• Ah, lunch time, so I would continue my comments this "Gloomy Locking Sunday Afternoon": youtube.com/watch?v=9dZj7YW5oFQ, 11,080,814 views 2012nov03. Cheers Aug 9, 2020 at 4:17

Modern ADCs use charge_balancing or charge_eating conversion methods.

That means the VREF must supply big hunks of charge, very fast, or the internal binary_search behaviors will make WRONG DECISIONS. The "very fast" means less than 1 nanosecond, or as fast as a tiny onchip FET switch can turn on.

So yes, you need a bypass capacitor on the VREF signal.

ADCs use approximately 10pF in their internal charge_eating. I'd make the cap at least

• 10pF * 2^number_bits

Thus for a 16_bit ADC, use 10pF * 2^16 == 10pF * 64,000 == 0.6uF

For delta_sigma (or sigma_delta) oversampling ADCs, the conversion system will grab many hunks of charge during any single conversion. See what the datasheet or the manufacture Apps Engr suggests.

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If you use an OPAMP to buffer the external VREF, ensure the opamp will not oscillate or have a RINGING response to those 1nanoSecond demands for charge.

To model this, you need to know the Output Inductance of the opamp. The datasheets do not tell you this. But some datasheets do specify Rout. And all opamp datasheets are proud to tell you the Unity Gain Band Width.

So let us use Rout and UGBW to compute OutputInductance. (The Output Inductance comes from the 90_degree_phaseshift of the 1_pole rolloff, and the constantly falling open_loop_gain).

We know Z_inductance = 2 * PI * Frequency * Inductance; re_arrange that, to find

• Inductance= Z_inductance / ( 2 * PI * Frequency)

Many opamps have an Rout of 100 ohms; some much higher (100,000 ohms for long_channel CMOS output devices; as low as 10 ohms or lower for fast bipolars). And since we want the VREF buffer opamp to quickly re_settle, have UGBW = 10MHz.

• Effective_Inductance = 100 ohms / ( 6.28 * 10MHz) = 100 / 63,00,000

• Effective_Inductance = 1/630,000 = 1.59 microHenries

And if you use an external 0.6uF cap, the Fring will be 1,000,000/6.3 = 160KHz

Now you want to dampen that. Will the 100 ohms Rout of opamp be adequate?

With the 10MHz UGBW opamp, Rout of 100 ohms, and Cexternal of 0.6uF, we have 35 dB peaking at 165,000 Hertz.

Using 1 ohm external between UnityGain opamp buffer, and a 0.6uF cap, we see (in Signal Chain Explorer) a 4.5 peaking at 150,000 Hertz.

Using 2 ohm external, and 0.6uF cap, we have 0.26 dB peaking at 90,000 Hertz.

Using 3.3 ohms (you can buy those), we have NO PEAKING, and are down 2.8dB at 100,000Hz.

Notice we now have a control_system design, with NO RINGING as the goal. And the present response is SLOW.

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Now let us use a FASTER opamp, and much smaller C_external, and larger R_dampen.

Use 100MHz opamp with Rout of 100 (1-0-0) ohms, and 0.01uF cap, and 1 ohm resistor. Notice the VDD bypassing on the opamp becomes a challenge and a part of the design, because at high frequencies, no opamp has any PSRR worth mentioning, so YOU must provide a very clean (well dampened) VDD.

With those params, the circuit (our magical VREF) has 11 dB peaking at 8MHz.

Let us increase Rdampen to 10 ohms (notice 10 ohms and 0.01 uF has 100 nanosecond time constant, needing 1,000 hanoSecond for 10 Tau settling which gives 87dB accuracy (10 nepers) on VREF.)

Result? NO PEAKING, and response is -1dB at 1MHz.

Notice a CLEAN VREF becomes a big deal. Of course, in a over_sampling ADC to get those 18/20/22/24 bit systems, you will have 100,000 samples of the VREF every second. Tho some audio quality ADCs with 192,000 conversions per second, seem to use well over 1Million input and VREF samples per second.

• $\mathrm{C=10p \cdot 2^{n}}$. Nice idea. Aug 9, 2020 at 8:24