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I am playing with SVCall function in ARMv6 using GNU gcc compiler

see below code with 2 defined SVCall functions ment to be compiled the same way:

void blinkFast(){
    while(1){
        gpio_toggle(LED);
        useless_delay_ms(50);
    }
}
#define SVC(code) asm volatile ("SVC %0" : : "I" (code))
//void SVCall_Handler(void){
    //__asm__ __volatile__("B %0\t\n"
                         //: /* outputs */
                         //:"rm" (blinkFast)/* inputs */
                         //);
//}


void SVCall_Handler(void){
    __asm__ __volatile__("B  blinkFast\t\n");
}

int main(void)
{
  mcu_init_stuff();
  SVC(0);
  while(1);
}

in the disassembly the first one gets assembled to:

b   #-76

while the second one is

b   #0  

according to my simple knowledge about gnu GCC this was original thought to use "I" constraint:

void SVCall_Handler(void){
    __asm__ __volatile__("B %0\t\n"
                         : /* outputs */
                         :"I" (blinkFast)/* inputs */
                         );
}

but i got the following compile error :

asm operand 0 probably doesn't match constraints
asm volatile("B %0\t\n"

and hence the only compiled one was "rm" constraint which gets translated to #0 in assembly.

what is the problem and how to fix it?

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  • 2
    \$\begingroup\$ Maybe you will get an better answer on SO. \$\endgroup\$ – Mike Aug 13 '20 at 10:53

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