stm32f401 usart: start bit detection sequence when oversampling by 8

I'm currently using usart on stm32f401. I'm wondering how the receiver detects start bit when oversampling by 8 is selected.

The reference manual (RM0368) states that the start bit detection sequnce is always the same despite the setting of OVER8.

2 explanations came up in my mind:

(1). If the start bit detection is exactly the same like what is shown in the image, and the sample clock frequency is stable, the received start bit will be 16 sample clock cycles meaning 2-bit long compared to other data bits in oversampling-by-8 configuration.

(2). Though oversampling by 8 is selected, when the internal circuitry enters "START_BIT_DET" state, the sample clock frequency will dynamically speed up to 2x, so the received start bit is still 1-bit long.

I've no idea how to explain this part of the manual.

• I've no particular idea, either. If I go by past experience I generally ignore the writing and focus on the graphs, tables, etc. The stuff that works in any language. This is because I've found that when there appears to be a disagreement (in the past) it always seems to be the English writing that loses out in the end and the schematic or picture is usually right. I'd just apply that here and assume that the author doesn't have English as their first language. State 0 until 1110 seen, then state 1 looking for 3 '0's of 5 bits, then either state 0 again or else state 2 looking for 3 '0's of 3. – jonk Aug 10 at 3:39
• Also, when transitioning from state 0 to state 1, if that happens, they skip one sampling clock and ignore whatever happens then. Maybe someone else can read this better than I, though. – jonk Aug 10 at 3:42
• @jonk I'm thinking about another thing. Unlike detailed design document, the user manual usually doesn't provide every aspect of how the logic will function. Telling the user how to configure the chip to do normal work is enough most of the times. Information on – Light Aug 10 at 3:59