I'm currently using usart on stm32f401. I'm wondering how the receiver detects start bit when oversampling by 8 is selected.
The reference manual (RM0368) states that the start bit detection sequnce is always the same despite the setting of
2 explanations came up in my mind:
(1). If the start bit detection is exactly the same like what is shown in the image, and the sample clock frequency is stable, the received start bit will be 16 sample clock cycles meaning 2-bit long compared to other data bits in oversampling-by-8 configuration.
(2). Though oversampling by 8 is selected, when the internal circuitry enters "START_BIT_DET" state, the sample clock frequency will dynamically speed up to 2x, so the received start bit is still 1-bit long.
I've no idea how to explain this part of the manual.