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I need to gate a TTL Tx pin @115000bps as the chipset that drives the RxTx lines do not implement UART BREAK for arbitrary time periods.

As a quick hack I have come up with the following configuration that I will connect to the TTL Tx pin of the said chipset, at TTL.TX.In.

enter image description here

The Tx output from the whole device will be tapped from TTL.TX.Out

BREAK is the gating input that controls whether TTL.TX.Out will be in BREAK condition or not.

The TTL levels can be ~5V DC or ~3v3 DC.

My questions are:

  1. What should be the proper value of Rb, Rbe and Re?
  2. Is this a proper design that will allow me to implement BREAK for arbitrary time periods without affecting the "usual" transmission?

My fears are:

  • i. The Vce drop, typically 0.7V can degrade the output signal quality (although I measured 0.05V Vce drop - are these old transistors that efficient now?)

  • ii. By driving the transistor too hard and @115000bps, the UART signal outputs could become severly degraded

Of course, in this case the transistor really should not affect TTL.TX.Out as it acts like a simple switch that either grounds TTL.TX.In or not, but I would like to ally any concerns that this design can cause problems down the line.

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  • \$\begingroup\$ Not an answer (that's why its a comment..): you want to be able to force a logic signal high. The simple solution for that is an OR port. Why the trouble with a transistor when you can just grab a chip with OR ports (or a single-gate chip if you are short on PCB space)? \$\endgroup\$ Commented Dec 17, 2012 at 21:00
  • \$\begingroup\$ @WoutervanOoijen: In my case a BREAK is logic low (~OV DC or GND level). OR would have been trivial to implement via diodes. \$\endgroup\$
    – vsmGuy
    Commented Dec 17, 2012 at 22:02
  • \$\begingroup\$ This design is faulty - it inserts a 0x00 at the beginning of the stream and "eats up" the last byte of the stream! \$\endgroup\$
    – vsmGuy
    Commented Dec 17, 2012 at 22:59
  • \$\begingroup\$ The question needs to specify the source voltage and currents when loaded to guarantee speed and proper interface to TTL. \$\endgroup\$ Commented Dec 18, 2012 at 19:52
  • \$\begingroup\$ @Richman: All devices are FETs except this "patch" and I have already specified the voltage to be 5V or 3v3. If I could have made the question better, please suggest how and I will edit it for benefit of others. \$\endgroup\$
    – vsmGuy
    Commented Dec 18, 2012 at 19:57

1 Answer 1

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No, your solution will affect normal transmission. When the collector of the transistor is driven low (while the "break" signal is high), the "break" signal will drive current through the two 1K resistors and the B-E junction of the transistor, holding the output (the emitter) at almost Vcc/2.

What you really want is an ordinary AND gate. When both inputs are high, the output is high, but if either input goes low, then the output goes low. Note that you can purchase single gates in SOT23 packages for applications like this. Look for the NC7SZ family from Fairchild, or the MC74VHC1GT family from OnSemi. This would be the preferred solution.

Since you asked, you can make an AND gate out of diodes, too (just reverse them from the OR configuration and use a pullup instead of a pulldown as a load). You could even use one of your NPN transistors as a dual diode. Also, you could use a second NPN transistor as an emitter-follower buffer, which would cancel out the level shift caused by the diodes. See below:

Circuitlab schematic

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  • \$\begingroup\$ Correct, I do need to implement an AND gate, but even a single gate will cost more than these transistors (I already have them in stock). What if I swap Re for Rc? That should limit the current and GND would be ~0.6V (or lower since I measured Vce to be ~0.05, which is unexpectedly low!) \$\endgroup\$
    – vsmGuy
    Commented Dec 17, 2012 at 21:59
  • \$\begingroup\$ Would you be able to elaborate on the options you mentioned, specially the "use one of your NPN transistors as a dual diode" part, or should I ask that as a new question? \$\endgroup\$
    – vsmGuy
    Commented Dec 17, 2012 at 22:58
  • \$\begingroup\$ Having been Eng Mgr at a major Contract Mfg, the SN74AHC1G08DCKR part in my answer will be < $0.04 assembled and tested in volume of 1K , which is lower than cost of all Dave's discrete parts even if parts are free. that would be my vote. not even counting the space savings of a SOT-25 \$\endgroup\$ Commented Dec 17, 2012 at 23:51
  • \$\begingroup\$ Just giving good advice to Dave in fair return \$\endgroup\$ Commented Dec 17, 2012 at 23:55
  • \$\begingroup\$ Dave - well, then how would this work in your opinion: circuitlab.com/circuit/gh3g6z/ttl_uart_gating_public \$\endgroup\$
    – vsmGuy
    Commented Dec 18, 2012 at 18:41

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