I'm designing a high impedance line tap for 10-10GBASE-T ethernet signaling. In the AFE I have a JFET LNA for high input Z which goes to a var. gain amplifier that is a fully differential ADC driver. I'm looking to have a flat passband from DC to 800MHz. The ADC has 100 ohm differential input and I'm controlling the characteristic impedance of the traces to match 100 ohm differential. The output impedance of many of the ADC drivers I've found all increase to 100-1k ohm at around a few hundred MHz. Surely this is going to cause reflections for the higher frequency components of the signal? Should I look into some passive impedance matching network? Even if I move the two chips close enough together I'd still have a large voltage divider past a few hundred MHz

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I forgot to add that there is an anti-aliasing filter after the var. gain amp. I am a current student and don't have too much access to simulation tools, but I do have LTSpice, MultiSim, and a full Altium Designer seat

  • \$\begingroup\$ Show the circuit please. \$\endgroup\$
    – Andy aka
    Commented Aug 10, 2020 at 15:51
  • \$\begingroup\$ I think your problem is more basic than reflections. If the output impedance of the ADC driver is really as high as 1 kohms, then you immediately have a 10:1 voltage divider, which is going to reduce the voltage into the ADC by 90% at some frequencies. \$\endgroup\$
    – SteveSh
    Commented Aug 10, 2020 at 18:53

1 Answer 1


The input capacitance of the JFET(s) will require charge form the line you are tapping.

You need to also define how much upset that line will tolerate.

A single pF at 1GigaHertz is -j 159 ohms.


If the ADC driver uses negative feedback, and has bipolar (silicon or SiGe) technology, the R_out should be 0.026/Iemitter_amps. Thus operating a class AB push_pull output at 5milliAmps should give an R_out of 0.026 / 0.005 = 5 ohms.

Perhaps provide link to your favorite ADC driver datasheet, and we can think further.

  • \$\begingroup\$ Sorry I should have added a schematic but all I have are broken block diagrams at the moment. I was wondering about the output impedance of the ADC driver not the input capacitance to the JFET. A low output Z from the driver is ideal to not voltage divide the signal, but as the frequency creeps up the bandwidth that I'd like to have a flat response in its output Z increases from about 0.1ohm to hundreds of ohms which I thought would voltage divide the signal and cause reflections? Is there a way to mitigate this increase of output Z over the BW? \$\endgroup\$ Commented Aug 10, 2020 at 17:12

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