0
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UPDATE: The issue with debugging someone else's code is you just have to assume everything is being coded correctly. I just checked datasheet and there was this BSY (bus busy) flag bit in status register. I just made it so that it waits for BSY bit to get reset and now the ~CS behaves properly. Sorry.

Working on TIVA-C 123GH6PM. Sending data over SPI lines does not produce the desired result. I am sending 3 bytes of data in one ~CS cycle and using the Freescale frame format. The ~CS line goes high before sending the last byte. enter image description here

If I send 2 bytes of data, the same thing occurs - the last ~CS goes high before I have the 8 clock cycles.

The only workaround I found was adding some delay before pulling ~CS high or sending another byte of data which of course doesn't get sent.

This is my write subroutine :

void SPI_write(uint8_t data)
{
    *(__IO uint8_t *)&SSI2->DR = (uint8_t)data;
    while((SSI2->SR & (1<<0))==0);
}

I tried type casting as you see above as I have worked on STM32 before and that has data packing, and typecasting there pulls ~CS properly, just as a last ditch effort.

Why does the ~CS line behave so strange? Is there a proper solution to solve this?

PS: I have selected the data size to be 8 bits just in case that comes out as a suspicion. If the full code is needed, I shall update the post with it,, just let me know

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  • 1
    \$\begingroup\$ Can you also post a scope trace of the data? \$\endgroup\$ – Lior Bilia Aug 10 at 21:47
  • \$\begingroup\$ What is the name of the flag bit you're checking in SSI2->SR & (1<<0)? \$\endgroup\$ – brhans Aug 11 at 2:55
  • \$\begingroup\$ Are you using SSInFss generated by the SSI controller for ~CS, or are you generating your ~CS in software with a GPIO write? \$\endgroup\$ – crj11 Aug 11 at 3:18
  • \$\begingroup\$ @crj11 I am generating my own GPIO write based ~CS as I wish to control when I send data. My slave device requires me to send 3 bytes of data in a single ~CS cycle. I have switched off alternate function mode on that particular pin too. \$\endgroup\$ – Luffy Aug 11 at 3:43
  • \$\begingroup\$ @brhans Checking if Transmit FIFO bit is empty. 1 = empty, 0 = not empty. It was to make sure all bits are transferred, and yet ~CS line forces the slave to not recognize that last byte of data. \$\endgroup\$ – Luffy Aug 11 at 3:46

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