# Design a circuit that detects if one input is a delayed version of the other

The above question has an answer, which I am not able to understand. I'll appreciate if anyone can guide me.I'm not able to understand the method used in the answer and procedure it went through.

Assuming 1b input A is generated by a random sequence, 1b input B is a delayed version of A. The delay value varies, and can be [1, 10] (inclusive).

Design a circuit, that takes A and B as inputs, and Y as output. If B is guaranteed to have 1s, then Y should be 1.

module dly_seq_dec
(
input               clk,
input               rst_n,
input               A,
input               B,
output logic        Y
)

logic [3:0] cnt;    // represent delay value up to 10

always_ff@(posedge clk or negedge rst_n)
if (~rst_n)
cnt <= ‘0;
else if (A | B)
cnt <= cnt + A - B;

assign Y = (cnt != 4’d0);

endmodule: dly_seq_dec


Obviously, “cnt” should be [0, 10]. If “cnt” > 10, then B is delayed for more than 10 cycles, and this is considered to be a spec violation. Designers should consider to have an SVA for this case.

If “cnt” < 0, then B is not a delayed version of A. This can happen when B sees a 1 but A never sees a 1. Designers should consider to write an SVA to detect the spec violation. In addition, “cnt” should be extended from 4b to 5b, and the MSB of “cnt” is for the sign extension.

• I'll modify my question and add the answer mentioned on the link via Screenshot. – Animesh Srivastava Aug 10 at 21:21
• Be quick........ – Andy aka Aug 10 at 21:24
• @Andyaka Done, please check. – Animesh Srivastava Aug 10 at 21:25
• The concept you're looking for is cross correlation. – Dave Tweed Aug 10 at 21:27
• You basically need to continually compare B with all of the allowed delayed versions of A, and keep track of which delay value(s) consistently show a match. As long as there's at least one, then Y should be asserted. – Dave Tweed Aug 10 at 21:51

The concept you're looking for is cross correlation.

You basically need to continually compare B with all of the allowed delayed versions of A, and keep track of which delay value(s) consistently show a match. As long as there's at least one, then Y should be asserted.

Note that there is no upper bound on the time required to detect a lack of correlation -- B might appear to be a delayed version of A for thousands of bits, until suddenly it isn't.

Here's some Verilog code that does what I described above. However, I'm not absolutely sure that this addresses the actual problem, because I don't understand the sentence, "If B is guaranteed to have 1s, then Y should be 1."

/* Do a cross-correlation between two signals to determine whether B is a
* delayed versions of A, with a delay in the range of 0 to N.
*/

module xcorr #(
parameter N = 10
) (
input         A,
input         B,
output logic  Y,
input         clock,
input         reset
);

reg     [N:0] A_delay;
reg           B_delay;

always @(posedge clock) begin
A_delay <= {A_delay[N-1:0], A};
B_delay <= B;
end

reg     [N:0] correlation;
reg     [3:0] count;

always @(posedge clock) begin
if (reset) begin
count <= N+1;
correlation <= {N+1{1'b1}};
end else if (count > 0) begin
count <= count - 1;
end else begin
correlation <= correlation & ~(A_delay ^ {N+1{B_delay}});
end
end

assign Y = |correlation;

endmodule


The shift register A_delay creates all of the allowed delays of A. We also capture B in B_delay in order to make checking the zero-delay case easier.

Each bit of the correlation register keeps track of whether we have ever seen a mismatch between B and the correspondingly delayed version of A. Therefore, it starts out set to all-ones, and bits are cleared whenever a mismatch occurs.

The counter is used to allow the shift register to fill up with valid data before we start checking. Once the delay expires, the output remains asserted as long as at least one correlator is still asserted.