# voltage to current converter using op-amp and MOS I came across voltage to current (V2I) converter circuit. and I found Iout=Vin/R1. I have a few questions about it:

1. I believe the op-amp is in the negative configuration because v(3) & v(2) both increase or decrease at the same time to make it negative stable feedback. If Vin increases, temporarily v(3) >v(2), thus output v(1) increases and lets NMOS to conduct more current, having higher I1 current than initial current across it, thus V(R1) increases and hence v(2) increases making it stable.

2. Intuitive, what is the output voltage of op-amp v(1)? if we have given LF sine wave at Vin? (I believe it'll be sine).

3. In which region does MOS operate? Is it linear? because we want Current to linearly follow Vgs. What I see is v(1) ~ v(R1) implies Vgs is almost 0, how does MOS even conduct and provide the required Iout=Vin/R1

4. If a capacitor C1 is placed in parallel with R1, we get a kind of LPF with a resistive divider(Ignore the name R1,R2 in the figure) where phase angle lags by 90 degrees at Higher frequencies, thus creating a possibility of instability(considering non-ideal op-amp also lags the phase), so we add a compensation circuit. How can I add a compensation network? How about attaching a phase lead compensator at v(1)? I think it won't be helpful since gate voltage would decrease in LF operation. But if it is so, how NMOS will allow the Iout amount of current?

• Why do you need to filter it ? and what f and -dB Is this to avearge PWM? Aug 12 '20 at 2:20

Your paragraph 1 is correct, as it is a feedback loop. MOSFET gate voltage cannot be calculated because it is in the middle of a feedback loop, and it depends on the MOSFETs uS value.

For the same reason the Vout of the op-amp is unknown without testing and recording its behavior. The MOSFET chosen will directly affect this value. Voltage-to-current tracking is very accurate as long as the op-amp inputs are in its common mode range and the MOSFET gate voltage is within specified Min - Max range. R1 at the source-to-ground has a limit of range. Too low and too much current will flow, thus a heat or power supply issue. Too high and you might exceed the MOSFET cut-off current.

All of this works very well when compensation is good enough and R1 has a tolerance of 0.1% if possible, so Vin (AC + DC) can be associated with a current value as accurate as a good DVM.

Because there is a 10 nF (typical but arbitrary) capacitor from op-amp output to the (-) pin, a capacitor across R1 could make the op-amp unstable and oscillate. If Vin is an AC signal plus a DC offset (to keep the loop stable) then accurate current modulation is possible, limited mostly to NOT cutting OFF the MOSFET, as this kills the feedback loop. HF modulation is possible, limited to the pass-band of the op-amp, including its output to (-) capacitor, which create a reaction (to changes in load or Vin) delay of 5 us to 100 us.

The output to (-) capacitor and a 10 K resistor in the feedback path are the compensation network. In fact it will NOT be stable until you add these parts. In any case HF modulation is limited to a few KHZ. The following schematic shows a simple compensation RC network, normally all that is needed. R1 100 ohms is placed at the gate of the MOSFET so trace is very short. simulate this circuit – Schematic created using CircuitLab

• Could you please explain how the output to (-) capacitor and a 10 K resistor is acting as a compensation network? Aug 12 '20 at 5:13
– user105652
Aug 12 '20 at 5:19
• Thanks for the schematic, I still do not understand how this will improve the stability. R2C1 network I mean. Talking about the voltage at V(R3), won't it provide 90-degree lag to the (-)pin at HF, thus leading to instability? Please correct me Aug 12 '20 at 6:27
• It adds stability because it is a low pass filter! The op-amp has internal HF compensation so at RF frequencies it is stable or has no gain. It slows its response to changes in load because the MOSFET responds much faster than the op-amp.
– user105652
Aug 12 '20 at 6:41

The FET is just a nonlinear voltage-controlled resistor, so the gate voltage will also be nonlinear relative to the current waveform due to the resistance divider created with the current sense R.

You always want to scale your control voltage to match the current sense voltage which for low power must be 50~100mV max in typical situations. So choose Imax then Rs.

This simulation should answer most of your questions,(and a few others you didn't ask) , except for phase margin stability with an LPF which is dependent on your Op Amp and filter specs not given, so not answered. But if you filter before the Op Amp, Vin+, that has no effect on stability. This 60mA LED has a resistance < 10 Ohms so your FET must also be << 10 Ohms to control the current give the output swing and 2.5x Vgs(th) to achieve low R in the linear region.

• what is the purpose of the 1K resistor? Aug 12 '20 at 5:10
• to add C for an RC experiment Aug 12 '20 at 6:46
• tinyurl.com/y5xwnhx3 Aug 12 '20 at 6:57