Is there a way to print the value of a signal using REPORT? I've seen report "" integer'image(a) for integers. Is there an equivalent for signals? Thanks

  • \$\begingroup\$ When you test bench your code, that shows you the states of all the signals your interested in. Or you could connect the signal a test pad output of the FPGA to see how it is responding. Why are you wanting to see a signal? \$\endgroup\$ – Puffafish Aug 13 at 10:08
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    \$\begingroup\$ But what if i have deeply nested components \$\endgroup\$ – Mark Henderson Aug 13 at 10:08
  • \$\begingroup\$ Then i will need to add to the ports in order to see the signal value? \$\endgroup\$ – Mark Henderson Aug 13 at 10:09
  • \$\begingroup\$ What's stopping you test benching the component you're having the issue with? You only need to test bench the component you want to look at. As much to save processing time as anything else. \$\endgroup\$ – Puffafish Aug 13 at 10:11
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    \$\begingroup\$ For example if i have an entity A which instantiates component A, inside component A instantiates component B, how can i see the signal values of component B? \$\endgroup\$ – Mark Henderson Aug 13 at 10:11

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