The below code gives me an error hat i cant read from out object Q
Im sure newer version of VHDL supports it, how do i enable in Vivado does anyone know?
Before i used GHDL compiler with a flag option
Or something similar to this
library IEEE; use IEEE.Std_logic_1164.all; --Non-gated SR latch, general configuration 2NORS --Only works when using the new VHDL version --Declare SR_Latch entity entity SRLatch is port( clk: in std_logic; set : in std_logic:='0'; reset : in std_logic:= '0'; Q : out std_logic:='0'; Q_n : out std_logic:='1' ); end SRLatch; architecture behavioural of SRLatch is begin process(clk) begin Q <= reset NOR Q_n; Q_n <= set NOR Q; end process; end behavioural; ```