The below code gives me an error hat i cant read from out object Q Im sure newer version of VHDL supports it, how do i enable in Vivado does anyone know? Before i used GHDL compiler with a flag option --use ieee=08 Or something similar to this

library IEEE;
use IEEE.Std_logic_1164.all;

--Non-gated SR latch, general configuration 2NORS
--Only works when using the new VHDL version

--Declare SR_Latch entity
entity SRLatch is
        clk: in std_logic;
        set : in std_logic:='0';
        reset : in std_logic:= '0';
        Q : out std_logic:='0';
        Q_n : out std_logic:='1'
end SRLatch;

architecture behavioural of SRLatch is

    process(clk) begin
            Q <= reset NOR Q_n;
            Q_n <= set NOR Q;
    end process;
end behavioural;

  • 2
    \$\begingroup\$ You don't need the latest VHDL version, VHDL-2008 will do. Try enabling VHDL-2008 support : Vivado may or may not support this 2008 feature (in 2020). In ghdl the option is --std=08 \$\endgroup\$ – Brian Drummond Aug 13 '20 at 13:52
  • \$\begingroup\$ The -2008 dependency is evaluating an output, which isn't supported in previous versions, requiring the use of mode buffer. Another issue may be the process is not synthesis eligible. clk isn't read in the process, while set , reset, Q and Q_n which are read and are not in the sensitivity list. See IEEE Std 1076.6-2004 RTL Synthesis (withdrawn) 6. Modeling hardware elements, 6.2 Level-sensitive sequential logic, Level-sensitive storage from process with sensitivity list "The process sensitivity list shall contain all signals read within the process statement." \$\endgroup\$ – user8352 Aug 13 '20 at 20:53
  • \$\begingroup\$ Note that I applied those changes to a bunch of my libraries and used VHDL-2008 and as far as I can tell, they continue to synthesize and operate properly however the simulation results are bonkers. I suspect VHDL-2008 might not be properly supported in simulation. Let me know if you see any different. \$\endgroup\$ – DKNguyen Aug 18 '20 at 4:40
  • \$\begingroup\$ Oh, I just found in VHDL 2008 for boolean conditions you can just have the signal name and boolean operators now. No need for an equal sign. So now you can go if (A or B). You don't need to go if (A='1') or (B='1') anymore. \$\endgroup\$ – DKNguyen Aug 29 '20 at 1:49

It never worked as far as I know. Not just in Vivado. Q is an output. You cannot read an output as you attempted with NOR. You can only write to it.

You could use inout, but this is dangerous. But best practice is to manipulate an internal signal and write that to Q.

But I believe you can set VHDL-2008 somewhere in the menu settings. Don't know about a syntactical way to do it though.

EDIT: It seems to be hiding in plain sight. It is set per source file in the "Source File Properties" window which is probably already open and just sitting in your regular layout in Vivado.

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Also from the Vivado manual starting page 203:


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  • \$\begingroup\$ "You cannot read an output as you attempted with NOR. You can only write to it." This has been an erroneous concept since the inception of VHDL, and corrected 25 years later by VHDL-2008. If you were to build the SR Latch out of discrete components, the net from the NOR output to the other NOR input would simply be a wire (a.k.a. lump of copper that has no concept of whether it being used as an input, output or internal net). If you were to put a scope probe on that internal net, it then becomes an output. In effect, you've added another wire to the internal net and called it Q. \$\endgroup\$ – tim Aug 13 '20 at 15:08
  • \$\begingroup\$ @tim Yeah. I was not aware of this was in 2008. Now that I am I can enable it and not do it anymore. It makes tapping off outputs to debug LEDs a lot more convenient. \$\endgroup\$ – DKNguyen Aug 13 '20 at 15:43
  • \$\begingroup\$ Of course in Vivado (at least 2018.2) you can complete simulation. get through synthesis, then find that the Reusable IP packager doesn't support 2008 and you have to go back and rewrite. \$\endgroup\$ – Brian Drummond Aug 20 '20 at 17:12

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