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I have constructed a circuit which uses two non-inverting unity gain buffers on one chip as stage seperation. I'm using a TL072CP chip with dual op amps on it and have followed the datasheet design for a non-inverting unity gain buffer. I'm having a problem whereby the output on both op-amps on the chip is giving what looks like an inverted signal of the inputs. The inputs are pulses generated from two seperate 555 timers, an output from one 555 timer feeds into the non-inverting input of one op-amp.

Single rail non-inverting unity buffer

In my circuit I measure the following signals (in red) at each of the pins. I've triple checked the connections and I am fairly certain that I haven't wired something up wrong.

Connections on board

When I measure on the non-inverting input terminal my input signal looks like this. The datasheet which gave the schematic above advised to ensure that the input voltage must be within the recommended common-mode range. The valid common-mode range is 4 V to 12 V and my input signal amplitude is 4.64V so I don't believe this to be an issue.

Non-inverting terminal input

Measuring on my output terminal shows this and the signal looks to be inverted

Output terminal

Could anyone suggest why this may be happening?

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    \$\begingroup\$ A very first step is to display both the input and output signal on the oscilloscope at the same time so that you can see the true timing relationship between the two. \$\endgroup\$
    – Michael Karas
    Aug 14, 2020 at 10:16
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    \$\begingroup\$ The lowest input voltage to meet the common mode conditions is 4V above VCC- and you appear to be feeding a signal that goes from 0V (out of spec) to 4.64V. The entire signal must be above 4V in your particular case. \$\endgroup\$
    – Peter Smith
    Aug 14, 2020 at 10:26
  • \$\begingroup\$ @PeterSmith Thanks for your reply. Is there a simple way that I could shift up the entire input signal by 4v so that this signal sits between 4v and 12v? \$\endgroup\$
    – Blargian
    Aug 14, 2020 at 12:18
  • \$\begingroup\$ The issue is that the amplifier has JFET inputs. Using a different type of amplifier would allow the signal to be used as it is. \$\endgroup\$
    – Peter Smith
    Aug 14, 2020 at 14:35

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If the valid common mode input voltage range is truly 4V to 12V (I did not check this myself) then it is necessary that your entire input signal swing must be between 4V and 12V. Your input signal looks to be at 0V on your scope trace most of the time and only goes into the valid common mode range when it has pulsed up to your ~4V level.

You should display both input and output at the same time and then compare the voltage level of of both during the pulse time to see what those levels are with respect to one another.

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  • \$\begingroup\$ this seems to be the problem. Is there a way I can offset the input signal so that it sits at 4V? \$\endgroup\$
    – Blargian
    Aug 14, 2020 at 12:27
  • \$\begingroup\$ There are ways to fix the problem but they may very well make the circuit more complicated. You may want to re-evaluate just what you are trying to do. Your input looks like a digital signal and if this is the case you should be using a digital logic buffer instead of an opamp solution. If you are truly with signals that are really in the analogue domain then you should really be looking for a better opamp that includes a common mode range that extends all the way to the -Vdd rail. They are out there! \$\endgroup\$
    – Michael Karas
    Aug 14, 2020 at 12:35
  • \$\begingroup\$ I added the opamp buffers because the circuit that those signals drive was distorting their shape and they were no longer square waves. I could probably just use those signals to drive the next circuit through BJT switches, would be easier than trying to shift the level. \$\endgroup\$
    – Blargian
    Aug 14, 2020 at 12:41
  • \$\begingroup\$ Lesson learnt to look at the common-mode input range and not to trust the simulator blindly! \$\endgroup\$
    – Blargian
    Aug 14, 2020 at 12:41

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