I need to gate a TTL Tx pin @115000bps as the chipset that drives the RxTx lines do not implement UART BREAK for arbitrary time periods.
Thanks to this community's feedback (Selecting proper vales of Rb, Re and and Rbe in a NPN transistor emitter follower configuration?) I have come up with the following configuration that I will connect to the TTL Tx pin of the said chipset, at TTL.TX.In.
The Tx output from the whole device will be tapped from TTL.TX.Out
BREAK is the gating input that controls whether TTL.TX.Out will be in BREAK condition or not.
BREAK is an output pin of a typical FET Microcontroller - say AVR, MSP430 or PIC.
The TTL levels can be ~5V DC or ~3v3 DC.
My questions are:
What should be the proper value of R1 and D1? (I am thinking R1 = 1K and D1 = 1N4148 but that is very arbitrary)
Is this a proper design that will allow me to implement BREAK for arbitrary time periods without affecting the "usual" transmission (When BREAK is off and all signals should go through)?
My fears are:
i. The Vf drop, typically 0.7V can degrade the output signal quality
ii. The 1N4148 is speced to work upto 4ns but it's capacitance is around 1pF and taking stray capacitance into account, I am not sure how the output signal would look like @115000bps.
Would you have reason to believe that the UART signal outputs could become severly degraded?
I have shared the schematic here. Feel free to make copies and modify it: https://www.circuitlab.com/circuit/gh3g6z/ttl_uart_gating_public/