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I'm learning basics of electronics and trying to get familiar with the common emitter topology. This is my schematic diagram:

Schematic diagram

When I try to simulate it in Kicad I get this:

Simulation

Everything works as I expect except the fact that "base" is 0.4V higher than "in". How this can be explained?

UPD. It looks like the voltage shift is not constant. If I change the capacitor and the resistor this way:

Schematic diagram 2

Thrn the voltages become equal soon: Simulation 2

It leaves me with question why these voltages differ by 0.4V initially? Is it something specific to ngspice?

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You don't have a fixed DC reference for the base, so the simulator is picking some number thats resulting from the internal transistor model. Try putting a 1 meg resistor on the base to ground, bet that mystery voltage disappears

Google 'bias BJT base' and you'll find the knowledge you seek :)

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  • \$\begingroup\$ even better if 1M pulls up \$\endgroup\$ – Tony Stewart EE75 Aug 15 '20 at 6:00
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Capacitor C1 breaks any DC connection between in and base.

You could add a 100 V (or -100 V) DC source in series with V2, and you’d get the same result for the voltage at base, at least after any start up transients die off.

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  • \$\begingroup\$ But it doesn't explain 0.4V shift in my simulation. \$\endgroup\$ – thesame Aug 15 '20 at 0:47
  • \$\begingroup\$ You don't have a fixed DC reference for the base, so the simulator is picking some number thats resulting from the internal transistor model. Try putting a 1 meg resistor on the base to ground, bet that mystery voltage disappears \$\endgroup\$ – Kyle B Aug 15 '20 at 0:58
  • \$\begingroup\$ @KyleB thank you! It pretty precisely answers my question. It would mark it accepted if it wasn't a comment. \$\endgroup\$ – thesame Aug 15 '20 at 1:05
  • \$\begingroup\$ Ok I made it an answer ;) \$\endgroup\$ – Kyle B Aug 15 '20 at 1:06
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Frankly, I was surprised to see a waveform at transistor collector...it should end up very near Vcc of 3.3V, with only a little squiggle of 10kHz.

Transistor base-emitter junction acts as a diode clamp, which only accepts current at the most positive peak of the AC waveform. This peak current biases the capacitor to a more negative average voltage after some long time.

An LTSpice transient simulation ran for 100 seconds, plotting from 99.999s to 100s (below). After this long time, collector waveform turns into a very short spike. Note that average base voltage (green) has fallen to nearly -0.5V...the base only conducts current for a brief moment at the +ve peak:collector and base voltage transient plot schematic

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  • \$\begingroup\$ Indeed, I can reproduce it on 100 sec interval too. Would a resistor between base and ground solve it? If so, how could I calculate its value? \$\endgroup\$ – thesame Aug 15 '20 at 3:25
  • \$\begingroup\$ Note I only suggested that base resistor earlier to demonstrate what happens when you fix the DC bias to something (in that case "gnd"). Your actual goal is to set a known DC bias at the base. You need to to that to get the transistor to conduct. The easiest, maybe most common, way is by a voltage divider between VCC and GND. youtube.com/watch?v=MNp-WxkF5h4 \$\endgroup\$ – Kyle B Aug 15 '20 at 3:43
  • \$\begingroup\$ Yes, @KyleB suggestion of a base-to-ground resistor can work. A DC voltage divider that biases base up closer to +0.6V is the better idea, especially if input voltage is a small amplitude. If you want to ensure that collector remains at Vcc when no signal (or small signal) is present, a diode clamp from base-to-ground is OK...with cathode connected to base. \$\endgroup\$ – glen_geek Aug 15 '20 at 12:06
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It's not perfect to make a sine to square limiter with a single transistor for variable input amplitudes.

For larger input when Vbe conducts more at 0.6V with lower impedance it clips and changes the DC bias offset.

New and Improved

But the best way is to use a pullup to Vcc,

  • Rb+/ Rc = 10 for pullup Rb+ (R+/R4)
  • Rc / Rs = 10 for serial input Rs (R4/R1)
  • then Rb+/Rs=100 with not much attenuation, yet better DC bias to base current.
  • V gain = Rc/rE until saturated the reduces a lot (towards 10% hFE) rE is base-emitter resistance

Once you learn these kind of impedance ratios, design gets easier.

enter image description here

Don't make the input cap RC=T too big otherwise the startup time can be too long.

Falstad SIM Tool

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