Why is this derivation of Schmitt trigger circuit's output signal, incorrect?

Question

This is the reference Schmitt trigger circuit. Using KVL, \$V_x\$ turns out to be \$\frac{R_1}{R_1+R_2}V_o\$. Also,

$$V_o = A\left( V_x - V_i\right)$$ $$V_o = A\left( \frac{R_1}{R_1+R_2}V_o - V_i\right)$$ $$\left( \frac{R_1}{R_1+R_2} - {1\over A}\right)V_o = V_i$$ $$V_o = \frac{V_i}{\left( \frac{R_1}{R_1+R_2} - {1\over A}\right)}$$

Since A is a very large number, \$\frac{1}{A} \to 0\$

$$V_o = \frac{V_i}{\left( \frac{R_1}{R_1+R_2}\right)} = \frac{R_1+R_2}{R_1}V_i$$

If \$R_1=R_2=1k\Omega, A=2\times 10^5, V_i=2\sin\left( \omega t\right) V, V_{cc}=3V\text{ and }V_{EE}=3V\$, then the graph would look like this (according to the above formulation),

A rough representation of input and output signals

In reality the output signal is completely different. I know how OP-Amp with positive feedback work. But I am just curious as to why the above derivation is incorrect. Particularly which step.

Answer 1

Point 1

The Schmitt trigger has hysteresis. Hysteresis implies that the circuit has memory. It remembers it last state. For a system with memory, you cannot write \$V_o = f(V_{in})\$. It should be of the format \$V_o = f(V_{in}, V_{o, \text{prev}})\$ or something equivalent._{As one of the comments mentioned below the question indicates, one would not know the system has memory the first time they try to solve the circuit using equations. IMHO, In that case, the following section would safeguard against an erroneous conclusion.}

Point 2

Output voltage being able to saturate is also an important feature since it prevents \$V_o\$ and \$V_x\$ reinforcing each other to infinity. Your equations do not model the saturation non-linearity.

Your second equation would have been better written as

\$ V_o = \min(\max(A(f(V_o) - V_{in}), -V_{max}), V_{max}) \$

With this scaffolding to represent the non-linearity, all further simplification attempted in the question would have been prevented.

edit

_{In response to OP's question below in comments.}

Let's analyse the case where \$V_{in} = 0\$. OP's second equation simplifies to

\$V_o = A(\frac{R_1}{R_1+R_2}V_o - 0)\$.

Neglecting the saturation, and for \$A\frac{R_1}{R_1+R_2} > 1\$, the solution to this system is

\$V_o = 0\$ or \$V_o = \infty\$ (since \$0 = A\frac{R_1}{R_1+R_2} \cdot 0\$ and \$\infty = A\frac{R_1}{R_1+R_2} \cdot \infty\$).

This means that, if the opamp output is forced to 0 and if there is no noise (or any other imperfection) in the system, the output remains there (OP's waveform also show zero volt output for zero volt input).

In a practical circuit, the output will be displaced from 0 volts by noise. So the question is, will the system remain there? Will the system move back to zero volt or \$\infty\$ volts? Dynamics (time evolution) of the system is not modelled by OP's equations, so, we cannot answer this question keeping ourselves to the algebraic equations where time is not modelled. If time was also modelled, I think we could have concluded that the 0 volt equilibrium point is unstable and the \$\infty\$ volt equilibrium (or \$V_{max}\$) is stable and system will have tendency to move towards the extreme output situation.

In short, using the algebraic equation above, we cannot analyse the this circuit when the output is not touching the saturation values (\$-V_{max} < V_o < V_{max}\$) since a practical system will have tendency to shift towards the saturation points and not lie exactly on the solution to the algebraic equation above.

edit 2

_{In response to comments below which ask to forget hysteresis stuff. I am attempting to construct an example without hysteresis}

Let me try to make a point with an analogy where an algebraic solution exists, but output is unbounded. This analogous system also has positive feedback. It too has finite output predicted by the equation. But output is unbounded.

The output-input relation is given by

\$ \begin{align} \frac{dy(t)}{dt} ={}& x(t) \color{red}{+} y(t)\\ (s-1)Y(s) ={}& X(s)\\ \frac{Y(s)}{X(s)} ={}& \frac{1}{s-1} \end{align} \$

For any finite amplitude sinusoid signal (including 0 frequency), the output predicted by the transfer function is finite. But the system will have unbounded output. The gain of this system as a function of frequency is same as the system \$\frac{1}{s+1}\$. I think this example forms a nice parallel to your example. No hysteresis or saturation was used in this example.

Answer 2

You made an assumption there's a stable output and calculated what the output should be in case the assumption is right. In addition you clipped the result to the possible output voltage range. The clipping is ok, but the assumption of the existence of stable output is not, as persons who know the feedback stability theory could confirm (see NOTE1)

People make same kind of reasoning continuously. Actually the whole physics is based on this kind of reasoning. There comparing to measurements is the way to reveal wrong assumptions.

NOTE1: there's no need to be an academic level mathematician or engineer to be able to make it clear a stable output can be achieved only because the limited voltage range clips the output. Some elementary Laplace domain analysis is enough.

If we assume there's some realistic slowness in the amp, say one RC charging and the gain is finite, maybe big, but finite we can find the transfer function for the whole circuit. Th slowness prevents infinitely fast changes so we can follow what the circuit does.

We can replace the ideal amplification A with G/(1+sRC) which is the transfer function of buffered RC integrator. G is the DC gain of the amp.

Let's also simplify the formula by replacing R1/(R1+R2) with a single symbol B. It's our feedback attenuation factor which is between 0 and 1.

The s-domain gain of the system is Vo/Vi = 1/(B-(1+sRC)/G)

Of course the output stays zero if the input is zero and there's no noise. But there's always some noise. We can find which s-domain frequencies start to ring in the system from the slightest pulse of noise by calculating which values of s make the denominator infinite (=find the poles of the transfer function). We solve s from equation (B-(1+sRC)/G)=0

The result is s=(GB-1)/RC

The Laplace transformation math says that the output from a slightest pulse of noise is proportional to an exponential voltage exp(t/T) with time constant T=RC/(GB-1). This T is positive as soon as GB is bigger than 1. Positive time constant means limitless grow which is in practice stopped only by the limited output voltage range. Negative T (i.e. GB <1) means that the ringing in the loop decays and the output stabilizes to the value which can be calculated with your original formula for Vo. But for a stable output A must be less than how much the feedback voltage divider attenuates.

Answer 3

Why does it look like an amplified clipped sine wave for Hysteric comparator using an Op Amp?

The GBW limits in Op Amps make poor high speed comparators since open loop they are just integrators with a LPF breakpoint near 10Hz or so.

Rise time is normally limited by output current into std load of 30pF. But in this case rise time is limited by internal compensation cap. So

If DC gain is Av=2e5 and GBW=4e5 then AC gain is only.
Av(f)<~2 estimated by your waves

So rise time , Tr is measure by 10~90% and f by -3dB point so f=0.35 You get Tr= 0.35 / f @-3dB

Just like your output.

All the hysteresis is correct.

Meanwhile positive feedback works as expected.

Suggestion

• use a logic gate or open collector comparator with 1k pullup and Rf=100k And Rin is the ratio if hysteresis. Then expect fast fall times but slow rise with xx pF loads.

• use a CMOS Schmitt trigger designed for 1/3 hysteresis

Answer 4

Circuit with hysteresis

First, I will comment on the memory properties of this circuit with hysteresis. Yes, it has memory... and it can act both as a Schmitt trigger and an RS latch.

Schmitt trigger. In these applications, the input voltage smoothly varies in both directions. The circuit behaves as a latch forced by the input voltage to stay in one of its two states. We take advantage of the sharp transitions and hysteresis to reduce various interferences.

Latch. In these applications, we toggle the circuit with hysteresis in one state or another by bipolar pulses (by changing for a moment the input voltage above/below the positive/negative threshold and then returning it to zero). The input voltage has three levels: Vin > +Vth (R), Vin < -Vth (S) and Vin = 0 (neutral). To make this latch behave again as a trigger, do not return to zero. This idea can be implemented by connecting the inverting input through a resistor to ground. The latch can be toggled by touching for a moment the input to VCC or -VEE .

More generally speaking, we can control a circuit with hysteresis in two different ways - by changing the input signal out of the hysteresis loop "without returning" (Schmitt trigger) and "with returning" (latch) it inside the loop (usually, in the middle).

RS latch

Then let's see if we can convert a latch into a Schmitt trigger.

RS latch with 2-input logic gates. The problem of this implementation is in its one-way inputs. The output voltage of the positive feedback and the input voltage are connected by a logic function (NAND or NOR) but not by an arithmetic function (summing) as in the case of the Schmitt trigger. That is why, once we toggle the latch through some of its inputs, we cannot toggle it back by the same input (it has lost its controlling function); we can do it by the other input.

RS latch with 1-input logic gates. There is no such a problem if the latch is implemented by 1-input gates (inverters) since they have 2-way inputs. A typical example is the RAM cell whose inputs/outputs can be controlled in both directions.

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As a conclusion, it seems we can talk about the use of hysteresis only in devices with one input (Schmitt trigger or a 1-input latch).