I'm trying to troubleshoot a piezo-driver circuit, which uses a PA84 op amp (10x gain). The schematic I'm working from indicates the supply voltages should be +200 / -15 V, which are well within spec... however, I'm getting a lot of noise on the output.
For example, looking at just CH2 in the schematic with no input signal, I'm seeing a threshold voltage for the DC bias input, where I move from virtually no noise (~ mV) to a lot of noise (~V) on the output. With the +200/-15 volt supply voltages on my op amp, the threshold is at about -1.5 V after the R45 pot (~30 V at CH2 out). I noticed, though, that reducing the V_s voltages to e.g., +100V / -15 changed this threshold so I could scan the pot R45 across its entire range without moving into a region of instability.
Has anyone encountered a similar issue before, or have any suggestions/pointers? It's not intuitive to me why the supply voltage would have such a noticeable impact on the op amp's stability... although to be fair, i'm very new to all this :P
NOTE: I also have a 4pf bandwidth-limiting capacitor across the op amp, in parallel with R19,R20,R21. This isn't on the JILA circuit posted online, but was necessary to get rid of serious op-amp oscillations. I've also put in a 10nF capacitor in parallel with R9, which was in a different (paper) copy of the same circuit given to me from someone who used to work at JILA (unclear why there is a discrepancy with the public domain circuit posted on their website...). The paper copy also shows a 3pF (not 4pF) bandwidth-limiting capacitor -- I'm using the 4pF one while waiting for the 3pF one to arrive. The circuit is also laid out on a PCB, and so there could be some issues with my design layout there...