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I'm trying to troubleshoot a piezo-driver circuit, which uses a PA84 op amp (10x gain). The schematic I'm working from indicates the supply voltages should be +200 / -15 V, which are well within spec... however, I'm getting a lot of noise on the output.

For example, looking at just CH2 in the schematic with no input signal, I'm seeing a threshold voltage for the DC bias input, where I move from virtually no noise (~ mV) to a lot of noise (~V) on the output. With the +200/-15 volt supply voltages on my op amp, the threshold is at about -1.5 V after the R45 pot (~30 V at CH2 out). I noticed, though, that reducing the V_s voltages to e.g., +100V / -15 changed this threshold so I could scan the pot R45 across its entire range without moving into a region of instability.

Has anyone encountered a similar issue before, or have any suggestions/pointers? It's not intuitive to me why the supply voltage would have such a noticeable impact on the op amp's stability... although to be fair, i'm very new to all this :P

NOTE: I also have a 4pf bandwidth-limiting capacitor across the op amp, in parallel with R19,R20,R21. This isn't on the JILA circuit posted online, but was necessary to get rid of serious op-amp oscillations. I've also put in a 10nF capacitor in parallel with R9, which was in a different (paper) copy of the same circuit given to me from someone who used to work at JILA (unclear why there is a discrepancy with the public domain circuit posted on their website...). The paper copy also shows a 3pF (not 4pF) bandwidth-limiting capacitor -- I'm using the 4pF one while waiting for the 3pF one to arrive. The circuit is also laid out on a PCB, and so there could be some issues with my design layout there...

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  • \$\begingroup\$ Re: unclear why there is a discrepancy with the public domain circuit posted on their website. Because people tweak stuff when they find problems, and neglect to update web pages. \$\endgroup\$ – Kaz Dec 18 '12 at 23:38
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If I were to guess, I would say that the circuit is falling victim to its wacky biasing scheme. A valiant attempt is made in the negative reference voltage generation to ensure good power supply rejection, with lots of bypassing (with capacitors of several sizes) and buffering. But this might not compensate for the op-amp being on wildly assymetric power rails. Everything in the datasheet assumes symmetric power rails.

Never mind that. Let's look at something else. In the specifications table in the datasheet we see something interesting under Common Mode Voltage Range. Namely, it can be as bad as plus/minus \$V_s - 10\$! Uh oh! This means that your circuit should ensure that the inputs of the PA84 do not go within 10 volts of either power rail. I suspect that the -VREF line alone could be violating that, even with no signal. Your manipulations of the potentiometer could be taking the device beyond the common mode input range.

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I won't pretend to know this specific circuit, but capacitive loads are a notoriously difficult problem for opamps...

Here is an application note describing similar stability problems and giving worked examples of solutions, which might be useful.

Edit : Reviewing the datasheet linked by Kaz, the "Stability" notes say:

2 . Keeping the external sumpoint stray capacitance to ground at a minimum and the sumpoint load resistance (input and feedback resistors in parallel) below 500Ω. Larger sumpoint load resistance can be used with increased phase compensation (see 1 above).

That would be R19..21 in parallel with R5,R18 - somewhere over 2k and certainly not below 500R. Increased compensation ( increase C5, reduce R1 ) may be called for. Current values look appropriate for a gain of 30 so already on the low side for a gain of 20.

Was someone trying to get a faster slew rate than the amp can comfortably provide? Does the application need the highest speed? If not, then just increase the compensation.

Re: supplies : the datasheet does indicate single-supply operation is acceptable, so I'm not worried about the asymmetric supply voltages. And if the -Vref supply is between 0 and -10V you should be within the common-mode input range at any setting of R45.

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Thanks for all the pointers! The problem turned out to be (somewhat paradoxically) that the circuit needed a small capacitive load. I discovered this almost by accident -- I never thought to look at the output on a scope and multimeter simultaneously, but when I connected my multimeter while the circuit was still hooked up to the scope, the op-amp stopped oscillating. Turns out the ~100 pF capacitance of the multimeter was enough to kill the oscillations, and soldering a similar cap across the output solved the issue.

I have no clue why this worked, because afaik capacitive loads are more likely than not to induce oscillations, not the other way around...

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  • \$\begingroup\$ I think it's because of the output impedance of the PA parts, which is reactive at certain frequencies due to the FET-based output stage. The datasheet discusses stability and gives suggestions for maintaining it. It looks like in your case the sumpoint resistance is larger than they suggest, which may be why it oscillated until you added an additional pole (which narrowed the bandwidth) with the extra capacitor. \$\endgroup\$ – Sean Dec 13 '18 at 19:04

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