Digital filtering after analog to digital conversion (ADC)

Question

I am making a PCB that receives a signal with a frequency band of 3-50 Hz and peaks of up to 10's of uV. I have implemented proper analog LP and HP (band-pass) filters and am using a 16-bit isolated ADC to send the data to a computer.

I am using Python to read the lines (derial communication) from the ADC (which is acting as a slave to my MCU.) The system diagram would look something like this:

^{simulate this circuit – Schematic created using CircuitLab}

When I get my data and do real-time FFT (since it is a non-stationary signal,) one obvious feature is a peak at 50 Hz (the mains has a frequency of 50 Hz in the UK,) and for that I can add a notch filter to reject the 50 Hz component, but that would mean extra cost and time to implement it.

I don't have much experience with digital filtering, but I was thinking, rather than implementing a hardware-based analog filter, is it possible to do the following procedure:

1. Perform the FFT.
2. Reject and suppress the 50 Hz component.
3. Convert the signal back into time domain.
4. Perform the analysis.

Will the time delay for this kind of filtering be just the number of machine cycles the computer goes thorugh to preform this task?

If this is plausible, is there anything that's wrong with just amplifying the signal and getting rid of the high frequency noises and spikes with a passive filter and performing all the mentioned filtering (notch, LP and HP) in the computer with Python or any other software methodology for that matter?

In terms of resolution, is it correct to assume that the final signal resolution under analysis is the multiplication of the resolution of the ADC by the digital filtering's resolution, since in my code values are saved as 32-bit floats?

Answer 1

If your wanted band is 3 to 50 Hz, then it will not be possible to notch 50 Hz out with any practical filter without losing some of the top end of your band.

Can you use a digital filter, or must you use an analogue one? It depends on the signal to noise ratio at the ADC. If your 50 Hz interference is at such a level it's causing you to turn the gain down before the ADC such that your signal becomes noisy, then you need an analogue filter before it. If you are getting both interference and signal through at an adequate gain without overloading the ADC, then you can use a digital filter after the ADC.

There is a trivially simple implementation of a 50 Hz notch that you can apply, either in the MCU or in Python, there's no need to use a relatively expensive FFT operation. If you add up samples over a period of 20 mS, then 50 Hz will be notched out. There is no need to do all of these adds for each output sample. It's more efficient to have a shift register that's 20 mS long and an accumulator, add the present sample into the accumulator, and subtract the sample of 20 mS ago.

This simple filter will give you a falling frequency response across your passband. Will it need correction before your analysis? It depends, what is your analysis, what is the specification on flatness across the band? The correction could range from the simple/bodgy process of adding a bit of slope to the response with a couple of taps, to designing a proper notch filter. The complexity of that task will depend on your sample rate, and your flatness and any group delay specification. IIR filters are good when there's some over-sampling, and no group delay specification.

Should you end up with an FIR filter that's more than a dozen or so taps long, it may be appropriate to use Fourrier convolution to implement it faster than the more naive multiply-accumulate approach.

Answer 2

You must use active guarding technique to eliminate CM 50Hz Ingress and achieve not as good CMRR as INA but good enough for EEG.

They call this Right Leg Guard or drive RLD. To use CM signals feedback to active body GND so that 50Hz noise is fed back to RLD.

Answer 3

Will the time delay for this kind of filtering be just the number of machine cycles the computer goes through to preform this task?

Yes it will add a delay. It really depends on if you need the data to be filtered in real time (with minimal delay). With real time digital filtering the delay is related to the speed of the processor, how long the processor takes to do multiply and add operations, whether the processor has to fetch memory for the FFT (you want the FFT to be in the processor cache to make the delay as small as possible, if it isn't then the processor goes to memory which can delay several clock cycles to fetch). You also may want to consider an FIR or IIR bandpass filter which can be much less computing resources for similar filtering.

If this is plausible, is there anything that's wrong with just amplifying the signal and getting rid of the high frequency noises and spikes with a passive filter and performing all the mentioned filtering (notch, LP and HP) in the computer with Python or any other software methodology for that matter?

Post processing the data is fairly easy with digital filters, the nice thing about it is digital filtering is it can be configurable via software. Analog filtering is not as configurable. The real question is: does the data need to be filtered in real time? (for control loops or other feedback, delays are bad so digital filtering can be a problem). An anti alasing filter before an ADC is a common way to reduce noise before it is sent to a computer.

In terms of resolution, is it correct to assume that the final signal resolution under analysis is the multiplication of the resolution of the ADC by the digital filtering's resolution, since in my code values are saved as 32-bit floats?

Digital filters can introduce quantization noise, calculating this noise is a whole science in of itself. Depending on the computing resources available conversion to doubles or floats can reduce quantization noise.