I have tried to google for this a lot but I can't seem to find anything.
You can infer block RAMs in three ways, depending on how much control you want.
altsyncramIP core, which allows you to specify all settings for the RAM directly (less inference, more control)
Verilog example (
"M9K"should be correct for Cyclone 10 LP, though it might be
(* ramstyle = "M9K" *) reg [0:7] my_ram[0:63];
-- First, declare a signal that represents a RAM type memory_t is array (0 to 63) of std_logic_vector(0 to 7); signal my_ram : memory_t; attribute ramstyle : string; attribute ramstyle of my_ram : signal is "M9K";
Rely entirely on the synthesis tool to guess:
reg [0:7] my_ram[0:63]; //Hopefully it will pick a block ram, but might use MLAB if small enough.