# How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.

• interference means disruption ... you may be using the wrong search term Aug 17 '20 at 20:25
• Please provide a description of your problem and re open your post. Aug 19 '20 at 18:20

You can infer block RAMs in three ways, depending on how much control you want.

1. Use the altsyncram IP core, which allows you to specify all settings for the RAM directly (less inference, more control)

2. Use the ramstyle attributes when you are declaring an array. How this is done depends on whether you are using Verilog or VHDL.

Verilog example ("M9K" should be correct for Cyclone 10 LP, though it might be "M10k"):

(* ramstyle = "M9K" *) reg [0:7] my_ram[0:63];


VHDL example:

 -- First, declare a signal that represents a RAM
type memory_t is array (0 to 63) of std_logic_vector(0 to 7);
signal my_ram : memory_t;
attribute ramstyle : string;
attribute ramstyle of my_ram : signal is "M9K";

3. Rely entirely on the synthesis tool to guess:

reg [0:7] my_ram[0:63]; //Hopefully it will pick a block ram, but might use MLAB if small enough.