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As I was reading the datasheet of STM32F103C8T6, I saw that it had 1.25 DMIPS/MHz (Dhrystone). What is DMIPS/MHz? I am adding the link to the datasheet here

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  • \$\begingroup\$ It's a measure of how many operations the CPU can perform in a single clock cycle : in this case, 1.25 on average, when Dhrystone is used as the test. \$\endgroup\$ – user_1818839 Aug 18 '20 at 12:25
  • \$\begingroup\$ en.wikipedia.org/wiki/Dhrystone#Results \$\endgroup\$ – Solomon Slow Aug 18 '20 at 13:35
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Dhrystone is a standardized speed test with a specific workload mix.

Different CPU architectures have different strengths and weaknesses. For example, a 75 MHz SPARC easily beats a 400 MHz PentiumII at AES, but loses in zlib decompression, so there is no way to tell which one is faster.

The Whetstone and Dhrystone tests are both synthetic tests that are useful mostly as a benchmark for scientific computing because of their composition, but there is no consensus on anything that is closer to a "realistic" workload, especially as realistic workloads for embedded devices will consist of a lot of idle time.

The result from a Dhrystone test is expressed in a unit of calculations per second, which does not necessarily correspond to actual CPU instructions per second, but is a tiny bit more comparable.

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Dhrystone is the name of a standardised a very old benchmark software, it gives as result the measured number of MIPS, where MIPS is Million Instructions Per Second. The figure was adjusted from long gone computers, but it doesn't matter.

1.25DMIPS/MHz means that your CPU will be 125MIPS at 100MHz

For example, it will be slower than a 1.8DMIPS/MHz CPU running at 80MHz

DMIPS is a very flawed measurement method for modern high performance CPUs, but it is still a bit relevant for small microcontrollers. (there is also CoreMark)

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    \$\begingroup\$ I'd like to add that one needs to be very careful when scaling DMIPS with the CPU frequency: just because you adjust a CPU core's frequency doesn't mean e.g. its memory bus frequency gets scaled by the same amount, neither does it apply inherently to RAM access latencies. It's really just "useful" as a marketing term. \$\endgroup\$ – Marcus Müller Aug 18 '20 at 9:23

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