possible CMOS techniques for altering the pulsewidth and phase shifting of a pair of complementary squarewave signals

My question is very simple in terms of input and output required. Following illustrations are for input and output:

input signals are a pair of complementary signals operating under 1MHz of speed. The way I though I could implement this was to reduce the pulse width of both signals, then shift them in time to produce the output as illustrated. What are the possible ways of implementing such CMOS block to produce that pair of output required, given the pair of input given as illustrated above? What essentially I need is that to not to let both inputs be ON at the same time. Any guidance is appreciated.

• What essentially I need is that to not to let both inputs be ON at the same time. I call that a break before make circuit but the signals are also called non-overlapping clocks. Use those terms to search in Google and add "circuit": "break before make circuit", look at the images tab and find plenty of circuits. Also, it is better to focus the question on what you're trying to achieve: not let the outputs be on at the same time instead of focusing on how that can be achieved: phase shifting using CMOS (phase shifting is not the way to do it). Aug 18 '20 at 15:51
• Looks like all you need to do is delay the rising edge slightly. Probably you can do this by feeding the input signal to a comparator with an RC delay. Bypass the RC delay with a diode so it only affects the rising edge, not the falling edge. Aug 18 '20 at 16:02
• @Bimpelrekkie Thank you for the reply. I did not mention in the question but I have already looked over those circuits. I also tried implementing "break before make" circuit in Cadence but however signals at the outputs still cross each other and if you look at the image I shared, you can appreciate i need significant (60ns) non overlapping time. non-overlapping clock generator circuits are mostly based on generating non overlapping signals making use of oscillators. But what I need here is clear, I already have the overlapping signals and have to use them to generate non-overlapping signals.
– Ams
Aug 18 '20 at 16:18

The dead time commutation method is used in all half bridge designs to prevent shoot through on any half or full bridge. The internal measurements are dependant on loading called propagation delay $$\p_D\$$. And deadtime.

It is often done with skewed rise/fall times internally using nonlinear R//diode:RC filters then limited.

You must define the back EMF duration time to protect this and it can span a wide range depending on load inductive current and L/R ratios. I often see 0.1% to 1% deadtime depending on speed of output stage.

So first define the loads and desired deadtime , the temp, V and tolerance variables and the entire RLC, clamp diode equivalent frequency Spectral noise response and efficiency of switch with SOA limits on VI power dissipation.

I see around 40ns deadtime on each edge with a 1us square clock period. normally high side is direction for a full bridge and bottom side is PWM for dual Nch drives so bottom side pumps the boost charge cap high side while regulating duty cycle of power.

Define worst, best case deadtime vs load. Design the delay times according to voltage and component threshold tolerances. once you define your limits your options will be clear.

E.g. normally rise times are << delay times for pre-driver

consider

• Use an 2 RC or LC delay lines buffered loaded for no overshoot each xx ns and use NAND Gates with 1st= early , 2nd = normal and 3rd = late pulse then NAND all 3 inputs and 3 inverted inputs to get reduced edges on each.

This was always done one original 5.25 HDD to compensate for bit shift on inner higher density tracks and called “precompensation design for HDD bit shift” . You can search for better solutions using this.

I have used 10% dead time using a Johnson counter at 10MHz for pulse shaping then ECL or CML for faster inverters depending on if you want synchronous full bridge or skewed. BUt you can now use 74ALCV inverters with 2ns PD