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I'm designing a PCB circuit for an amplifier to amplify a pulse with a rising time of 1 ns about 100 times.

I decided to use the Analog Device AD8000 as op-amps.

This is the schematic of one amplifier. The single board consists of six amplifiers placed row by row accepting six input signals.

schematic

In the above figure, I have cascaded one amp in non-inverting configuration (x10) and two in inverting configuration (x10, x3). The impedance values for one input and two outputs are set to 50 ohms to match with LEMO coaxial cable.

The values of feedback resistors are referred from the manual.

When I soldered only one amplifier circuit and tested it (because I had failed and failed with my prototypes wasting a lot of expensive op-amps,) it worked well as I expected.

However, after soldering one more amp (consisting of three AD8000), all output signals oscillate.

I tried cutting out the ground plane below the input and output pads of the op-amps and adding a feedback capacitor to the non-inverting and the inverting configuration to reduce the stray capacitance but it didn't help to prevent oscillation.

I think it is not a problem of parasitic capacitance in that it works with a single amplifier circuit. It seems to that some kind of interaction between the sensitive nodes of op-amps through R1 or R13 (in the figure) connected to the ground plane makes it oscillate.

Can anyone explain why this oscillation happens and how to deal with it?
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Let me provide layers of 4-layers PCB. Please note that the it is actually connected in the red box.enter image description here

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  • \$\begingroup\$ 40 ohms is loading the first stage to the 2nd stage virtual earth point. This seems excessive. Why didn't you go for non-inverting gains for 2nd stage and 3rd stage (reference your picture)? \$\endgroup\$ – Andy aka Aug 19 '20 at 14:31
  • \$\begingroup\$ Did you also solder the decoupling capacitors? Have you used the "magic touch" (i.e. touch the circuit) to see if you can change the frequency of oscillation? Also, not sure if it matters, the AD8000 datasheet Rev. C lists the AD8003 as "under development". \$\endgroup\$ – Sven B Aug 19 '20 at 15:18
  • \$\begingroup\$ The 40 ohm register value for inverting is referred from the manual and they recommend not to deviate 10 percent from the recommended value. I have tested with a single stage of inverting and non-inverting and found that output of non-inverting amp has a DC offset component.<br/> Yes, I also soldered decoupling caps and "Magic touch" didn't have any effect on the circuit. Thank you for information of AD8003, it is saied the development has been finished. I will consider replacing with it after resolving the problem. \$\endgroup\$ – Hyunmin Yang Aug 19 '20 at 23:32
  • \$\begingroup\$ See link for impedance for typical track widths for PCB thicknesses, electronic-products-design.com/geek-area/electronics/pcb-design/… . \$\endgroup\$ – BobT Aug 26 '20 at 1:49
  • \$\begingroup\$ Ideally use a track width comparable to the SMD footprints (0603 parts are 0.76mm wide). Using layer1 as a ground plane will produce low impedances (i.e. capacitive compared to the resistors hanging off that track) Using layer 3 as a ground plane near the SMA connectors should produce a more sensible track width. also the feed to the two output SMA's should be run with tracks angled at 45degrees, you have a lot of kinks in your tracks. \$\endgroup\$ – BobT Aug 26 '20 at 1:49
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Congratulations on progressively tackling a very challenging system and circuit.

You have SIX channels, with

  • 1 nanosecond Trise (160MHz 1-pole bandwidth)

  • Gain of 1,000X (60dB) as 10 * 10 * 10 (into output coax splitter)

  • Bandwidth (per the ADI datasheet) of about 150MHz for gain = 10X (20dB)

  • large output currents into dual coaxes

while using 3 stages of the AD8000 that has

  • 14 milliAmps Iddq

  • 100 milliAmps output current

  • Power Supply Rejection Ratio at DC of about 60dB (for 1 volt out, need 1000 volts on either +VDD or -VDD

  • Power Supply Rejection Ratio at 100MHz of about 20dB (for 1 volt out, need 10 volts on either +VDD or -VDD)

  • Gain of +1 ==> 1,500MHz, Gain of +2 ==> 600MHz, Gain of +10 ==> 150MHz

  • PowerDown pin located adjacent to Feedback pin (some coupling between)

Without viewing the PCB layers, or viewing the oscilloscope waveforms, let us strive to create ideal performance in each stage. With excellent stage_level operation, we may be able to solve the "oscillation" rather simply. Let us work thru this.

Points To Ponder

  • My first thought, as I read your goals (lotta gain, very fast circuit) is --- --- how is he isolating each opamp's VDD (+ and - ) from the other opamps' VDDs

And I notice all the opamps (6+ of them, right) in at least 2 signal_chains of 1,000X, are sharing a common +5v, and sharing a common -5v.

SO LET US STOP SHARING THE VDDs

  • Use an Exacto knife, cut the traces between the local bypass caps and the global VDD.

Make 6 cuts for each signal_chain. And then solder 1 ohm SMT resistor across each cut. This will cost you 0.014 volts, so your opamps now will operate at 4.986 volts.

TO REPEAT, INSTALL SIX NEW RESISTORS into each signal_chain in the VDD+ and VDD- traces.

These resistors ensure a huge reduction in Power Rail interaction.

Why is this important? The AD8000 is a fine opamp, but at high frequencies the PSRR (as with all opamps) is weak/low/inadequate, and you must assist with external PCB LOW_PASS_FILTERS.

The external circuit is not a Low_Pass_filter UNLESS you insert some substantial SERIES impedance.

FERRITE BEADS are not dependable. But 1 ohm resistors are dependable, at all frequencies.

And 1 ohm resistors are guaranteed lossy, at all frequencies.

Also add SMT capacitors on the GLOBAL VDD+ and on the GLOBAL VDD-. Have at least 0.1uF + 10uF to provide instantaneous high output current needs.

Notice, using Q = C * V, differentiating to get dQ/dT = C * dV/dT + V * dC/dT and simplifying to I = C * dV/dT, that

your typical VDD upset, as your final opamp strives to drive 3 volts into 50 ohms, or 60 milliAmps, for 10 nanoseconds, from 10uF charge storage, has the delta_VDD being

dV = I * dT/C = 0.06amp * 10nanoSec / 10uF = 0.06 * 0.001 = 60 microVolts VDD upset

which enters the opamp to encounter Gain = 1,000X to become 60 milliVolts, and is about 30X smaller than what we assumed (3 volts output into 50 ohms).

SO VDD as a feedback path ---- may not be the cause.

However, as this schematic has ALL VDD capacitors in parallel, let us examine the effect of PCB VIA inductance or bypass_cap inductances or non_zero trace size. Assume 10ma at 100MHz, coming thru 1nanoHenry. At 100MHz, that is 0.6 ohms times 0.01 amps = 6 milliVolts. Scaling 6mV by 1,000X, you have 6 volts output. This ignores any benefit of high_frequency PSRR, which is about 20dB or 10:1.

Summary: the VDD as feedback, with inductance in the bypass caps or vias or traces as problem, is indeed viable.

Adding the 1 Ohm resistors may be the solution.

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Can you provide the PCB layout of all layers?

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DOES THE MANUFACTURER ENCOURAGE floating the Enable pin?

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Added Aug 25

By sharing ONE VIA at each VDD bypass point, one of the two caps has a LONG ground trace, in addition to 1mm (1 nanoHency) of trace from other cap to the via.

Thus one cap has about 4 nanoHenry inductance, and the other cap has 2nH inductance.

Why not have 2 vias, perhaps shared, but place each via near the GND termianal of each cap.

Particularly for the output OpAmp in each Signal Chain, driving 1volt? into 50 ohms at 100 MHz??, that 20milliAmp thru 4 nanoHenry at 100MHz produces

  • Vring = L * dI/dT = 4nH * (0.02 amp / ( 1/( 2 * PI * 100MHz)) )

or

  • Vring = 4nH * [ 0.02 amp / 1.6 nanoSeconds (slewrate) ]

or Vring = 4nH * [ 0.02 /1.6nSec ] = (nano cancel) 0.02 * 2.5 = 0.05 volts

VDD trash ringing is 50 milliVolts (at bottom of VDD bypass caps, 3rd opamp).

That 50 milliVolts ringing, at bottom of the VDD bypass caps, is "shorted" to the top of the 2 caps (of the 3rd opamp) and then thru 2nH or 3nH to the VDD plane (or "E" finger +VDD and -VDD distribution structure (I like how you did that)).

The capacitance of the "E" fingers is about 5cm by 1cm (times 3), with spacing of 0.02" (0.8mm) with relative dielectric constant of 4.7 (call it 5).

  • Capacitance [VDD+ or VDD-] ~ 9e-12 farad/meter * 5 * (3 * 5cm * 1cm)/0.8mm

  • Capacntace_VDD = 45e-12 * 3 * 50mm * 10mm/0.8mm * 1meter/1,000mm

  • VDD_capacitance = 45e-12 * 150 * 12.5/1,000 ~~ 45e-12 * 2 ~~ 100 pF

NOW .. what is the resonant frequency of 100pF (either VDD structure, spaced 0.8mm from the dual Ground planes?

  • Capacitance = TWO_planes * 100pF = 200pF

  • Inductance (from output OpAmp VDD) = 2 nanoHenry.

Using Fring_MHz = sqrt(25,330 / (L_uH * C_pF)), we have

Fring = sqrt(25,330 / (0.002 uH * 200pF)) = sqrt(25,330 / 0.4) = sqrt(62,500)

F_RING_OSCILLATE = 250MHz

If we include the physical distance from the 3rd opamp, back to the first opamp, and double that for sqrt(Er_FR-4), and double again for a full cycle of ring/oscllate, we add about 4" or about 400 picoSeconds delay.

Which summed with period of 250MHz, becomes about 200MHz.

And 200MHz is not far above the 160MHz of each stage in a 10:1 gain config.

Now is the 0.05 volts ringing on the VDD "E" enough?

Assume PSRR ar 100MHz is 20dB (10:1). That gives us 50/10 = 5 milliVolts Referred To Input (RTI), into a gain=1,000 SignalChain, to produce 5 volts output, and we only assumed 1 volt output.

So yes, VDD ringing (because of Via & PCB_trace & CAP_ESL (and ESR?) of level of 0.05 volts, coupled WITH NO ATTENUATION ONTO the VDD "E" structures, does compute to be a problem.

Nicely, adding attenuation between the LOCAL OPAM VDD bypass caps and the GLOBAL VDD, in the form of lumped resistors, seems a good method. Notice we don't know what a randomly chosen FerriteBead will do for us. But we know a 1ohm (or 10 ohm) resistor will work/attenuate at all frequencies.

And 1 ohm (with 200pF "E" capacitance is only 200pS LPF tau, so may NOT be adequate to reduce the central shared VDD "E" structure ringing.

Your value of TEN OHMS ---- seems to be REQUIRED.

==================== summary of why oscillates ========

  • high gain amplifier that shared VDD on all 3 gain stages

  • high output current (into 50 ohm?)

  • inductance in the Ground path of bypass caps (4+ nanoHenries)

  • gain of 1,000 out past 100MHz

  • Power Supply Rejection that is low (20dB? or less) at 100MHz

So with 1 volt output at 100MHz, we have 0.05 volts VDD ringing; that becomes 0.005 volts RTI into first stage; after gain of 1,000X we have 5 volts output.

And with so much phase_Shifts and delays, the SignalChain finds a way to satisfy Barkhausen.

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Thanks to BobT for the bypassing comments.

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Thermal noise (Boltzmann) maths

At 240 ohms Rnoise (total input noise density model), with gain = 1,000 and bandwidth of 100MHz, the voltage_generated output noise (RMS) will be

  • 2 nanoVolts/rtHz (240 ohms) * Av=1,000 * sqrt(100,000,000 Hz)

  • 2nV * 1,000 * 10,000 = 8nV * 1e+7 = 8 * 1e-2 = 0.08 volts RMS broadband from voltage noise

The current noise (the non_inverting multiple_emitter input) is about 30 picoAmps rms. The Resistance is 40 ohms external. The bandwidth is 100MHz.

The broadband noise is 30pA/rtHz * sqrt(100,000,000) = 30pA * 1e+4 , or 300 nanoAmps. Converted to voltage, we have 0.3uA * 40 ohms = 12 microVolts.

Scaled by voltage_Gain of 1,000Z, th eoutput noise is 12 milliVolts.

We RSS combine 80mV and 12 mV, getting about 80 milliVolts RMS.

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  • \$\begingroup\$ Thank you for answering my question. I found that adding 10 Ohms register(of the smallest value I have) to all positive and negative Vdd in series remove the oscillation up to with 3 channels soldered. I couldn't test with all 6 channels soldered because I accidentally shorted GND and Vdd when cutting the traces for the fourth channel. I'm going to design and order a new PCB board. I'll come back with the full result. The manufacturer doesn't say anything about floating the Enable pin but I also think it is safe to connect it to GND. I appreciate helping to resolve my problem. \$\endgroup\$ – Hyunmin Yang Aug 24 '20 at 2:30
  • \$\begingroup\$ That's a good detailed answer, I typically use two vias straddling the GND pad on my decoupling caps for HF design. A 20dB PSRR combined with a total gain in excess of that is asking for trouble. \$\endgroup\$ – BobT Aug 26 '20 at 0:46
  • \$\begingroup\$ A good calculation of stray inductance too , At a previous place of employment we had a PhD design a laser diode driver circuit for typically 10A at 5ns into a laser diode from a 12v nominal supply, on his first attempt he recorded 1000Amps across his 100milli-ohm shunt, technically it was a damped sinusoid, swinging plus and minus 1000Amps. His current shunt was an axial resistor!. \$\endgroup\$ – BobT Aug 26 '20 at 0:57
  • \$\begingroup\$ (continued) I redesigned the whole thing, we had to fabricate some 8ohm transmission line (from really thin, flexible PCB) , and used a whole bunch of SMD resistors in parallel for current sense, coupled to a SMA connector with a 50R resistor, then we got a whole lot more light out!, and the current waveform matched the light output., \$\endgroup\$ – BobT Aug 26 '20 at 0:57
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I suspect you have too much capacitance to ground around the input pins. Particularly layer 1 , which will have a very small dielectric thickness to the input pins. and also output pins, layer1 should look more like layer 4 (ground plane) See page 15 of the data sheet. page 15 data sheet

Capacitance between + and - inputs and from + and - inputs to ground can cause oscillations in ordinary opamps.

The other contributor is inductance on the input tracks, so shorter, thicker tracks are recommended.

Capacitance to ground on the output can also cause oscillation, and again layer 1 is probably to blame. Swapping the interstage R25 and C25 around might make a difference, as the amplifier would then be seeing a more resistive load (however you just be moving more stray capacitance to the next op amp).

Layer 2 (power layer) could also be contributing to capacitance, why have you left big holes under each IC on this layer?, would seem more sensible to run the power tracks under the IC, leaving the areas under the IC pins open. I would run the power tracks left to right, just above and below each IC. I would also be sprinkling ferrite beads around a bit too.

Have you contacted Analog Devices? I found them very helpful on issues like this, we had a high performance design with a "new" op-amp that oscillated due to stray capacitance between the inputs, we contacted AD and they were very helpful, we just swapped to a different op-amp and all was fine, it was just that particular op-amp was a bit more sensitive to input capacitance. They modified their spice circuit for the part, and the oscillation will show up using the modified spice circuit.

The area around the input connector does not conform to good RF practice, and certainly not for 1nS risetime, the tracks are too long and wind around a bit. There seems to be some kind of 3 way jumper for testing, that will behave as an inductor / antenna.

The power supply distribution is not typical of good RF or low noise analogue design , the power should be brought in from right to left , so power direct to the rightmost IC , then a ferrite bead to the middle IC with a bypass right at the pin, from here a ferrite bead then to the left most IC with a decoupling cap right at the pin. You only need the 10uf cap at the rightmost stage. There are other relevant comments on power distribution in another answer,

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