# Modelling a positive edge triggered T flip flop with asynchronous clear

I am modelling a positive edge triggered T flip flop with asynchronous clear. Here is the code :

module t_flip_flop_exam (q,clk,clear,t);
input t ;
input clk;
input clear;
output reg q ;
reg internal_t;
always @ (clear)begin
if (clear==1)
q=0;
else
q=q;
end
always @ (posedge clk)begin
if (t==1)
q=~q;
else
q=q;

end

endmodule


Is this is an efficient code? Is it ok to have to separate always blocks, or is there is a way to include both the clear and the clk signals behavioral code in a single always block?

## 1 Answer

This is a common way to combine the always blocks:

module t_flip_flop_exam (q,clk,clear,t);
input t;
input clk;
input clear;
output reg q;

always @(posedge clk or posedge clear) begin
if (clear)
q <= 0;
else if (t)
q <= ~q;
end
endmodule


It is better to make assignments to a signal from a single always block.

Trigger the always block on the posedge of clear so that synthesis can infer the desired logic (asynchronous clear, synchronous toggle).

Use nonblocking assignments (<=) for sequential logic.

There is no need to explicitly do q=q because it is implied.