I am currently trying to configure my board to take an external square wave from a function generator, measure the time interval between rising and falling edges, then output the measurement on screen.

I am not sure how to add external signals to the board or how to monitor the output measurement. I've attached a picture of the board from Microsemi's website.

enter image description here

I am quite new to FPGA programming and all I have done with this board so far is simulate basic counters, filp-flops and blinked an LED on the board.

Thanks for the help!


Here you have schematic for this board: https://www.digikey.com/eewiki/download/attachments/64422068/DIGIKEY%20MAKER%20KIT%20REVA1_0_20170606.pdf

According to schematic (sheet 6), J7 header pins 3,4,5,6 are connected to some FPGA pins which i assume you can use as GPIO's.

  • \$\begingroup\$ I see the area you are talking about. Does it not matter which is input and output as long as I assign the according pins to my verilog code? \$\endgroup\$
    – yer
    Aug 19 '20 at 21:21
  • \$\begingroup\$ You can configure any pin output or input what you need. \$\endgroup\$ Aug 19 '20 at 21:28
  • \$\begingroup\$ @BerkerIşık From the picture that I attached in my original post, there is a pin that has a copper square around it. Is this ground? \$\endgroup\$
    – yer
    Aug 19 '20 at 22:31

The board you use is not very important, the important thing is how you do the work. Use a simple state machine and measure the period first.

  1. Check your clock frequency. For example if it is 50MHz, you have 20ns resolution.
  2. Detect a high signal and start counting until a low signal.
  3. You detected a low signal in step2 and start counting until a high signal.
  4. Switch between steps 2 and 3. Calculate the period using your resolution.
  5. Use USB or Ethernet or if exist Logic Analyzer inside your FPGA to send or display the period with unit second. Simplest way use UART over USB and read the value any termimal like putty, teraterm ..

in VHDL sketchy

case state is  
when h:  
count_l <= 0;
if (wave='1') then  
count_h <= count_h + 1; 
out_h <= count_h;
state <= l;  
end if;  
when l:  
count_h <= 0;
if (wave='0') then  
count_l <= count_l + 1;  
out_l <= count_l;
state <= h;  
end if; 

I didn't use the board before but I guess it doesn't have user accessible gpio pins. You can use maybe soldering a small cable to buttons on the board.
The code above just symbolic for more accurate calculation use higher clock frequency and signal cleaner inside the FPGA.

If there is a problem, please ask without hesitation.

  • \$\begingroup\$ I am not sure how to read your VHDL since I only use Verilog. Could you write out each block? I have already done steps 1 and 2 that you suggested, but the one issue I am worried about is how to reset the counter from a previous measurement and store the measurement so it can be displayed. \$\endgroup\$
    – yer
    Aug 19 '20 at 21:31
  • \$\begingroup\$ When leaving a state, assign your count value to output or another signal. In state1 reset low period count and in state2 reset high period count. This provide storing actual values before a transition from a current state to a new state. \$\endgroup\$ Aug 19 '20 at 21:54

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