I cannot seem to understand this. Please explain the Kvl part for this as well.
Current will only flow through Rg during start up, due to the reason that the gate of a mosfet is capacitive, except for extremely small leakages of course.
So when the circuit of yours reach steady state the current will stop flowing through Rg to the gate of the mosfet.
There is an insulator (like glass) between the gate and substrate (the two parallel lines in the symbol of the MOSFET M1) so that the input circuit is broken. The resistor Rg is connected with its upper end to the drain and its lower end is "floating" (unconnected). There is no current flowing through it... so there is no voltage drop across it. The gate voltage is equal to the drain voltage... as though the drain is short-connected to the gate. So you can safely remove Rg...
If you want to know how this circuit operates, here is a possible intuitive explanation. M1 compares its drain-source voltage with its "input" threshold voltage Vth by subtracting them and changes its drain current to make the difference between them zero.
I repeat it again since such an explanation is not so popular - the treshold voltage Vth serves as a "constant input voltage" for this voltage stabilizer with voltage-type negative feedback. Such a configuration - a transistor (MOSFET here) whose drain is connected to its gate, is known as a "diode-connected transistor" or "active diode". Its main property is to keep up an almost constant drain-source voltage when the drain current varies.
The "sandwich" of two "plates" and insulator between them is actually a small capacitor that is charged/discharged during the transitions of the input voltage. So, a small pulse current enters/exits the gate at these moments. But this is not the case in this analog circuit where there are no transitions.