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always @(posedge clk)
       count = count+1;

and

   always @(posedge clk)
           count <= count+1;

what difference do the above codes have in simulation? I get that the synthesis will yield the same result, but what changes occur for one-line assignment simulation when using blocking and non-blocking assignments. A similar question was asked some while ago here. But I am not satisfied with the answer there, and since I am low on reputations, I could not comment there. Please note that I know the difference between blocking and non-blocking assignments. I just need to know the difference when it comes to one-liners.

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  • \$\begingroup\$ In complete isolation, no context at all, and where there is only one statement in the always block? I'm not sure anyone can help much. But this EESE link carries discussions that may help you, more broadly. \$\endgroup\$
    – jonk
    Commented Aug 21, 2020 at 16:53

1 Answer 1

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The difference has nothing to do whether there is one one line or a block of code. If count is being read by another process synchronized to the same positive edge of clock, you have a race condition as to whether you're reading the new or updated value.

This code could be in the same module or connected to another module.

always @(posedge clk)
         zero = (count == 0);

Although synthesis treats this as "zero will be true the the cycle after count is 0", zero might get ahead by one cycle in simulation if it reads the updated value to soon.

You should my recent post "SystemVerilog Race Condition Challenge Responses"

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