I am laying out an ADuM260N digital isolator. There is some higher frequency switching (~20MHz) on other components also connected to the input (left) voltage rail. I read this thread on decoupling, but there doesn't seem to be any consensus on the best via layout, specifically whether to connect the vias to the IC pin or the capacitor pin.
After reading the grounding sections of Ott's Electromagnetic Compatibility Engineering, two takeaways are:
- Add multiple vias to power/ground to reduce loop inductance
- Reduce mutual inductance by spacing out vias carrying current in the same direction (eg. GND and GND), and by moving vias closer that carry current in opposite directions (eg. PWR and GND)
From these takeaways, my attempted layout is below:
This is the datasheet's recommended layout:
From this, I have a few questions:
- Should I be connecting the vias of the 5V nets to the IC pin or to the capacitor pin?
- Could using two vias per net in this way somehow harm EMI/EMC performance?
- Is the datasheet recommendation of connecting the decoupling capacitor GND across the IC directly to the GND pin of the IC, a good idea?