I realise this verilog code isn't ideal, and later on I might ask for general review somewhere but at this time I'm not looking for general review except so far as it affects the issue I have (unless they whole thing is fundementally broken of course, then I want to know!). I realise the timing probably isn't quite right, and hard coded numbers etc are likely bad, it's just a first attempt to learn, and my problem is understanding the warning at the moment.
I'm trying to make a VGA output on a papilio pro. It's somewhat working if I just output the vertical and horizontal sync but when I try to output the rgb signals I get this warning :-
WARNING:ConstraintSystem:119 - Constraint <NET "vga_r" LOC="P78" |> [main.ucf(6)]: This constraint cannot be distributed from the design objects matching 'NET "vga_r"' because those design objects do not contain or drive any instances of the correct type.
WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "vga_r" LOC="P78" |> [main.ucf(6)]' could not be found and so the Locate constraint will be removed.
module main(input clk_32, output vga_hs, output vga_vs, output vga_r, output vga_g, output vga_b); wire clk_50; // Use a clock generator IP module to make a 50MHZ clock for the VGA clkgen clock_gen(clk_32, clk_50); // Current scan line number reg[0:9] row_count; // Current pixel position in scan line reg[0:10] pixel_count; always @(posedge clk_50) begin if (pixel_count == 1599) begin pixel_count <= 0; if (row_count == 524) begin row_count <= 0; end else begin row_count <= row_count + 1'b1; end end else begin pixel_count <= pixel_count + 1; end end // Set "on" only during the visible part of the screen wire on; assign on = (pixel_count > 112 && pixel_count < 752) && (row_count > 12 && row_count < 492); // Assert the hsync and vsync pins during the proper parts of the video frame assign vga_hs = ~(pixel_count < 96); assign vga_vs = ~(row_count < 2); // Just turn on the R,G,B outputs during the main area of the screen for now. assign vga_g = on; assign vga_b = on; assign vga_r = on; endmodule
and my UCF file contains this which I think is correct...
NET "clk_32" LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; NET "vga_vs" LOC="P99" | IOSTANDARD=LVTTL; NET "vga_hs" LOC="P97" | IOSTANDARD=LVTTL; NET "vga_b" LOC="P92" | IOSTANDARD=LVTTL; NET "vga_g" LOC="P80" | IOSTANDARD=LVTTL; NET "vga_r" LOC="P78" | IOSTANDARD=LVTTL;
clkgen is a clock generator generated by the tools and appears to be working correctly.
I don't undersdtand what the warning is telling me, it appears to be preventing the synthesis from working though. It all looks right to me but I'm clearly missing something, can anyone see what I'm doing wrong? (And be gentle I'm new to verilog!)