std_logic has a resolution function
Not only does
std_logic have more useful states besides
0, it also has a resolution function defined.
A resolution function is a VHDL language concept. It is a function that is associated to a type, and it determines what happens when multiple values of that type are applied to a single signal. The syntax is:
SUBTYPE std_logic IS resolved std_ulogic;
std_ulogic is the unresolved (and thus much less useful) version of
In particular, this implies nice things like
1 leads to
entity std_logic_tb is
architecture behav of std_logic_tb is
signal s0 : std_logic;
s0 <= '0';
s0 <= '1';
wait for 1 ns;
assert s0 = 'X';
This makes intuitive sense, as we understand
X to be the state where multiple incompatible values are applied to a single wire.
std_logic also knows how to resolve every other possible pair of input signals according to a table present on the LRM.
bit on the other hand, does not have a resolution function, and if we had used it on the above example, it would lead to a simulation error on GHDL 0.34.
The possible values of
std_logic are a good choice because they are standardized by IEEE 1164 and deal with many common use cases.