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I want to buid an ocsillator out of discrete XOR gates, I want to acheive 80MHz.

I've tried building one from SN74LVC2G86, but rise/fall times I get is about 25ns. Datasheet does not specify the rise/fall times for this part, but in recommended operation conditions it gives numbers like 10ns/V @ 3.3V - this somewhat agrees with my measurements.

Is stray capacitance on my board affecting the circuit or is LVC family not good for a task like this?

This is my circuit and PCB:

enter image description here enter image description here

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    \$\begingroup\$ You don't state what the issue is. Are you having problem hitting 80 MHz? Also what are the values of R1,R2 and C3? Typically you want 180 degrees phase around the loop (meaning an odd number of inversions). \$\endgroup\$ Dec 20, 2012 at 19:25
  • \$\begingroup\$ I agree. LVC isn't what you're looking for. It seems you know what the issue is and what you need to solve it. \$\endgroup\$ Dec 20, 2012 at 19:58
  • \$\begingroup\$ XOR gates do not have the best symmetrical on propagation delays. Ask yourself, what frequency stability do you need over supply and temp, what phase noise, what is the equivalent noise bandwidth or effective Q of the resonator, the report back. Perhaps relaxation is adequate or ring oscillator or better LC tuned OSC with temp comp. and best performance and lowest cost is a 50 cent XTAL with gate osc and PLL multiplier. on a chip. \$\endgroup\$ Dec 21, 2012 at 2:47
  • \$\begingroup\$ If hitting 80 MHz is important to you then get a pre-canned oscillator. Just apply power and GND and it'll spit out 80 MHz. If you want to learn how to make oscillators out of gates then don't try getting 80 MHz and don't expect it to stay within about 30% of the frequency you intend. \$\endgroup\$
    – user3624
    Dec 21, 2012 at 15:55

2 Answers 2

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LVC isn't a good part for this. Any logic family isn't. There is just too much variation in manufacturing process, temperature, and voltage to get a repeatable frequency.

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Yes, at high frequencies, the parasitic stray capacitance has a big effect.

The normal way to produce a high frequency clock these days is to keep all the high frequency stuff inside one chip, typically with a clock multiplier -- a phase-locked loop (PLL) including an on-chip high-frequency variable-speed oscillator, phase-locked to some multiple (or some fractional ratio) of an off-chip crystal, where the crystal is running at some much lower speed.

If I just wanted an 80 MHz oscillator, I would use such a PLL or perhaps simply buy some off-the-shelf canned 80 MHz oscillator.

If I wanted this to go faster, and I wanted to learn something new, there's lots of things I could try:

If you want to push ahead with a discrete implementation, I'm sure you will find it very educational.

  • Perhaps connecting the 3 gates in some other arrangement might go faster? Perhaps connecting them as a 3-inverter ring oscillator?

The schematic you show is normally used with "unbuffered inverters". ( a b c d e f ). I might try to pick a real "unbuffered inverter" chip -- perhaps something about them would make it work better than wiring up an XOR as an inverter?

If for some reason I really wanted to use an XOR gate, I might try to pick some chip that inherently ran "faster" -- i.e., it has a smaller tpd, also called the tPLH,tPHL, also called the propagation delay.

  • The MC10EP08DTG datasheet specifies a tpd of 320 ps. That XOR gate is over 10 times as fast as the specification in
  • The SN74LVC2G86 datasheet specifies a tpd of 3.6 ns at VCC = 5 V (worse/slower at lower voltages).
  • The NC7SV86 datasheet specifies a tpd of 3.3 ns at 2.70 ≤ VCC ≤ 3.60 (worse/slower at lower voltages).
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  • \$\begingroup\$ I agree that propagation time affects maximum frequency I can achieve, but in this particular case my problem is slow rise/fall time. \$\endgroup\$
    – miceuz
    Jan 11, 2013 at 11:38

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