Trying to measure a pulse width and then send pulse of same width using Verilog [closed]

Question

I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods that the input signal is high. I can then take the last number from this counter and multiply it by the clock time period to get the time that the input pulse was high.

The issue I am running into is how to store the count from the previous pulse, generate the return pulse and start measuring the next pulse so that its return pulse can be generated. I know I need to incorporate some type of delay but I am not sure how long the delay should be.

Here is the code and simulation result I have so far.

///////////// HDL Code //////////////
module counter    (
out     ,  // Output of the counter
in_1  ,  // input signal
clk     ,  // clock Input
reset   ,     // reset Input
);

  output [7:0] out;
  input in_1, clk, reset;
     
  reg [7:0] out;
  reg [7:0] counter;
    
always @(posedge clk)
if (reset) 
  counter <= 8'b0;
else if (in_1) 
  counter <= counter + 1;
else if (in_1 == 8'b0) 
begin 
  out = counter; 
  counter = 8'b0;
end
endmodule 

///////////// Test bench Code //////////////

`timescale 1ns/100ps

module counter_tb;

//parameter SYSCLK_PERIOD = 20;// 50MHZ

reg clk_1;
reg in_11;
reg reset_1;

wire [7:0] out_1; 

initial
begin
    clk_1 = 1'b0;
    in_11 = 1'b0;
    reset_1 = 1'b1;
    
    #20;
    
    in_11 = 1'b1;
    reset_1 = 1'b0;
    
    #50;
    
    in_11 = 1'b0;
    
    #100;
    
    in_11 = 1'b1;
    
    #100;
    
    in_11 = 1'b0;
    
    #50;
    
    $stop;
end

//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always
    #5 clk_1 = ~clk_1;


//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  counter
//////////////////////////////////////////////////////////////////////
counter counter_0 (
    // Inputs
    .in_1(in_11),
    .clk(clk_1),
    .reset(reset_1),

    // Outputs
    .out( out_1 ),

endmodule 

Answer 1

You don't need to measure the output pulse, you just have to set it high for the same number of clock cycles.

One way to do this would be to have two separate counters, an input counter and an output counter. The input counter could count up from 0 as you are already doing. Whenever you are done measuring the input count, you could then use that to set the initial value of the output counter. Then every clock cycle, have the output counter count down, stopping at 0. Set the output signal high whenever the output counter value is nonzero.

You could also possibly use the same counter for both input and output (count up while measuring input, then count down for output), but it will probably be a little trickier to handle all the corner cases properly.

By the way, when you say "I can then take the last number from this counter and multiply it by the clock time period to get the time," I just want to make sure you mean just for a debug output. You don't need to do this multiplication within the design itself.