I'm wondering if anyone has used the open-source Nangate library to do synthesis and post-synthesis simulation? I was trying to synthesis my processor and got the netlist verilog file from design compiler. Then I tried to simulate it using modelsim but it seems that my circuit was never initialized by reset. So I tried to instantiate the model DFFR_X1 directly check the simulation. Here is the testbench, DFFR_X1 is the flip flop module from the library:

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And here is the simulation result, note the weird Stx signal when the circuit is being reset.

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But at least output is right after reset. For my processor, outputs that are resetted by reset signal stay at Stx:

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So I look into the library and find the module description for DFFR_X1 and I notices this:

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where ng_xbuf is defined like this:

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RN is the input reset signal, I don't understand why the library connect this input port to a output port? To compile my design and the library, I did:

vlog NangateOpenCellLibrary.v

vlog out.v (netlist verilog)

vsim -noglitch my_toplevel_module

and run the simulation the same way I did for RTL code which works perfectly fine. I also tried to let design compiler produce a sdf file and feed it to simulation but still didn't work. I'm really stuck here so please if you can give me any suggestion on what can be improve or other commands I can try. The full verilog library can be found here:


Thanks a lot!


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