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I am designing a 2 layer PCB that doesn't deal with high speed signals or high currents (sensor board communicating over Lora via SPI and I2C) but does have a LoRa (900MHz) RF daughter board to one corner very close to the power source.

My board has ground planes on both sides but also signals on both. I am trying to keep signals to one side as much as possible, but there are some mechanical constraints that tie my hands a little.

So to make the grounding as good as possible, I am adding vias connecting both ground planes as much as I can and eliminate potential ground islands. I am laying them out in a grid with 3mm between the vias and 0.2mm drill.

But I am wondering if both from an electrical engineering point of view, and a cost point of view, is it "the more the better"? Or does adding a lot of ground vias add cost to PCB manufacturing, or is there an EE drawback to adding a lot of ground vias?

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    \$\begingroup\$ At higher speeds via's have capacitance that may need to be accounted for. Is your power supply switch-mode? What frequency does it operate at? Are you able to follow the LoRa layout guidelines for the board, regarding what can/cant' go under the antenna? \$\endgroup\$
    – Ron Beyer
    Aug 28, 2020 at 2:21
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    \$\begingroup\$ 3mm grid does not sound excessive. But you can move some or add extras to pick up odd shaped almost islands (larger careas connected to the GND fill with a thin bottleneck shape). \$\endgroup\$
    – user57037
    Aug 28, 2020 at 3:17
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    \$\begingroup\$ 3mm grid is perfectly fine... \$\endgroup\$
    – citizen
    Aug 28, 2020 at 9:03
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    \$\begingroup\$ The cost of a via is very, very small. Even in very low cost high volume products, it is not usual to worry about the cost or complexity of adding vias. \$\endgroup\$
    – user57037
    Aug 28, 2020 at 15:19
  • \$\begingroup\$ To address some comments: the lora board is a separate board (rfm95w) and has an external antenna so I don't think it'll introduce any issues. The only traces underneath it on the same side are 3 gpio interrupt pins from itself, and the rest is ground plane. \$\endgroup\$ Aug 29, 2020 at 7:30

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Make a sketch of the two sides, of their "GROUND" regions, using two different 0red/blue) pencil. If any region is poorly (skinny trace) connected into your GROUND graph, then try to move components and widen the connective traces.

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