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I have a 6 layer PCB that is populated on both sides. The PCB mainly consists of power supplies (PoE, battery charger, buck converter) and a uC and a controller. The Layer stackup is: TOP Signal - GND - Power - Signal - GND/Signal - Signal Bottom.

At some areas, the GND, PGND and BATGND are overlapping on different layers (mid-layer 1 and 4). However, I made sure that the components directly above the ground layer are corresponding to the correct ground.

Do you think this could be much of an issue?

enter image description here

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  • \$\begingroup\$ IMO there is much an issue regarding all other islands that have the gap exactly in the same position, I would do it similarlyl as building a house with bricks. But I am a noob in PCB manufacturing. \$\endgroup\$
    – Marko Buršič
    Aug 28, 2020 at 11:01
  • \$\begingroup\$ More basic question is why do you think you need the 3 separate GND sections? If the return path for a signal has to cross gaps in a return plane, or has to cross planes, this can be worse than just having a single return (GND) plane. \$\endgroup\$
    – SteveSh
    Aug 28, 2020 at 13:20
  • \$\begingroup\$ Also, have you traced out the signal flow path (out and back) for your critical high speed/fast edge rate signals? \$\endgroup\$
    – SteveSh
    Aug 28, 2020 at 13:21
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    \$\begingroup\$ For a 6-layer PCB there seem to be too many ground sections on too many layers, IMHO. Generally speaking one should allow for one dedicated system ground layer as the main ground plane. You may consider another layer on which you require say, an AGND island section for particular components, or a sepparate PGND section. These ones you can isolate but they still require, eventually a single low impedance return path to the main system ground plane... \$\endgroup\$
    – citizen
    Aug 28, 2020 at 13:36
  • \$\begingroup\$ The reason for the different ground sections is because they are required as per IC data sheet. Battery charger IC and Buck module have dedicated GND and PGND pins ans datasheets state to use net ties. BATGND is required as current is measured over a shunt connecting PGND and BATGND. There are only a few "high speed" signals for an etherner phy on the left top side, they are taken care of. All the other signals are pretty low frequency. As said, mainly power supplies on this board. \$\endgroup\$
    – F. Heisenberg
    Aug 28, 2020 at 14:32

2 Answers 2

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AppNotes

Unfortunately, far too often you'll find a lot of non-sense in AppNotes. The fact that a package has both an ANGD and PGND does NOT mean that you have to have separate grounds for them.

AGND/PGND

What it does mean is that internal to your IC (inside the package) an AGND and PGND coexist, which you should be tied together to one (common) ground outside the package, on your PCB. Separating grounds is a very risky business and is not required in 99.99% of cases. Some very sensitive analogue circuits and audio stuff require it sometimes.

When is a signal high-speed?

The criteria for a signal/IC to be considered high-speed is NOT clock frequency. It's signal rise-time. Most of today's ICs have rise-times in the region of 100ps-500ps nominal, which means a bandwidth of ca. 700 MHz -3.5 GHz. That is high-speed! You can easily fail with a 1 MHz clock if your rise-times are short!

References

I highly recommend you watch Rick Hartley's How to Achieve Proper Grounding talk on YouTube.

Two books I'd also recommend are:

  • Signal and Power Integrity - Simplified by Eric Bogatin
  • Right the First Time Vol. 1 & 2 by Lee Ritchey
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  • \$\begingroup\$ Yes the energy is in the field and what not. Realized this also a year ago, watched that Rick Hartly grounding video (who didn't?), read a couple books, and of course changed the design to only have one ground plane. I should update that way outdated question when I have time. But thanks for the answer ;) \$\endgroup\$
    – F. Heisenberg
    Jun 25, 2022 at 11:00
  • \$\begingroup\$ Glad you found it helpful! If so, would you mind accepting my answer (by clicking on the tickmar next to it)? \$\endgroup\$
    – pfabri
    Jun 26, 2022 at 14:19
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Realize that each ground has some small resistance and inductance ~5 nH/cm that may not seem like much, but then some circuits may want to be high SNR or isolation on the order of 40~60 dB or more.

Each layer will have some capacitance that will couple crosstalk if dV/dt exists from current surges to high impedance inputs.

Without going thru a signal analysis, you might be lucky or not. Do you feel lucky? If not examine the effects of high impedance inputs if a surge step load runs under it. Use Saturn PCB Design.exe to estimate your capacitance, (ballpark) based on overlap area and gap with some tbd mV rise in ground voltage.

Mutual inductance works on current for low impedance inputs and outputs.

The wandering gaps have a smaller capacitance but some, due to the electrode cross-sectional area of copper thickness.

Consider f-3dB=0.35/tr for your upper frequency ( ignoring harmonics) from some L/R or RC rise time =Tau , not exact but close enuf.

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  • \$\begingroup\$ With "Saturn PCB Design.exe", do you mean their Saturn PCB Toolkit"? Also, what donyou mean with wandering gaps? \$\endgroup\$
    – F. Heisenberg
    Aug 31, 2020 at 10:14
  • \$\begingroup\$ Your boarders are wandering \$\endgroup\$
    – Tony Stewart EE75
    Sep 2, 2020 at 0:28
  • \$\begingroup\$ if you look at battery charger EVM, they also have overlapping PGND and GND and therefore wandering gaps: ti.com/tool/BQ24800EVM \$\endgroup\$
    – F. Heisenberg
    Sep 2, 2020 at 7:44
  • \$\begingroup\$ The wandering is not a concern but the XYZ capacitive coupling is inversely related to gap and proportional to parallel area times the rate of change of voltage. the idea is to isolated CM crosstalk of grounds conduct noisy spectrum from Analog references in case of imbalanced input Z \$\endgroup\$
    – Tony Stewart EE75
    Sep 2, 2020 at 13:13

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