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I am connecting together two "LVDS" devices. The specs are as follows:

Output: VoDiff = 247-600 mV, Vcm = 1-1.485 (1.25 typ)
Input: VinDiff = 100-500 mV, Vcm = 1-1.6 (1.25 typ)

So for the most part they look compatible. However I am wondering if I should be concerned that the output can swing up to 600 mV and the input is rated up to 500 mV. Is this a concern?

The input has two 50 ohms to GND with a mid voltage of 1.25. So I am guessing I do not need any termination, but just concerned about the voltage swing.

LVDS receiver - Teledyne e2v EV12DS480A 12-bit, 8 GSps DAC

LVDS driver - Xilinx Kintex UltraScale XQRKU060 FPGA. Please see p.27

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  • \$\begingroup\$ "the output can swing up to 600mv and the input is rated up to 500mV. Is this a concern?"... if your transmission path consumes the 100mv difference at minimal output current of your transmitter - No \$\endgroup\$
    – schnedan
    Commented Aug 28, 2020 at 16:20
  • \$\begingroup\$ @schnedan This is not how LVDS works. It's a current loop that drives a current into a 100 ohms load. \$\endgroup\$
    – asdfex
    Commented Aug 28, 2020 at 16:46
  • \$\begingroup\$ Too short for an answer: There shouldn't be a problem if you use proper termination and the maximal voltage on either of the wires is always lower than the receivers input driver voltage. But details may depend on the specific devices. \$\endgroup\$
    – asdfex
    Commented Aug 28, 2020 at 16:50
  • \$\begingroup\$ @asdfex I worked with an LVDS based System for 10years... I know what I say \$\endgroup\$
    – schnedan
    Commented Aug 28, 2020 at 17:00
  • \$\begingroup\$ Under what condition(s) is the VoDiff = 247-600 mV specified? LVDS is a constant current, +/- 3.5 mA drive. When terminated in 100 ohms (typical for high speed diff interfaces), this gives us the nominal Vdiff of +/- 350 mV. The only way the input would see greater than 350 mV diff voltage is with a parallel termination of 170 ohms or greater. \$\endgroup\$
    – SteveSh
    Commented Aug 28, 2020 at 18:21

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