I am using a division module which has two signals other than inputs "go" to indicate start of division. "done" to indicate stop of division. It is taking approx 300 clock cycles for the division to complete

How do I stop the rest of the circuit from executing while this is being done?

I have to generate the following code

if x>p

The division here is taking 300 odd clock cycles to complete and I have to stop the assignment of m until value of c is calculated from division thanks for the help :-)

  • \$\begingroup\$ Please add more details about your questions to avoid any down votes and flags! Add code, and describe your problem more. Also indicate what you have done to resolve the issue by yourself. Thanks. \$\endgroup\$ – Chetan Bhargava Dec 21 '12 at 6:18

Create a state machine where it will be stuck in a particular state until done signal asserts.

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In cases like these, your divider module is usually considered part of the datapath/dataflow of your design. All modules should include some kind of 'enable' or 'clken' signal so that the control fsm can coordinate when and where data flows. When the modules are cascaded with each other with no controller, then they usually have some sort of flow control mechanism, such as a vaild/ready pair.

If the other parts of your circuit were not designed this way, you can usually implement it by gating their clocks (this is not possible in certain cases though, like when they contain a pll). This is a way of giving them the 'enable' funcionality that you are looking for.

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