How to generate wait until division is over in verilog?

I am using a division module which has two signals other than inputs "go" to indicate start of division. "done" to indicate stop of division. It is taking approx 300 clock cycles for the division to complete

How do I stop the rest of the circuit from executing while this is being done?

I have to generate the following code

if x>p
c=-p/x;
m=(c+10)f
else
c=-x/p;


The division here is taking 300 odd clock cycles to complete and I have to stop the assignment of m until value of c is calculated from division thanks for the help :-)

• Please add more details about your questions to avoid any down votes and flags! Add code, and describe your problem more. Also indicate what you have done to resolve the issue by yourself. Thanks. – Chetan Bhargava Dec 21 '12 at 6:18